In order to shorten the time of characterization analysis of SoC products, Cypress has developed a characterization analysis bench platform similar to ATE level, called CyMatrix, using NI PXI source measurement units, PXI matrix switch modules and FlexRIO modules. Let's take a look at how Cypress performs testing.
4x parallelism has significantly reduced the time required for characterization, which allows us to identify and fix bugs faster. The new characterization system has directly reduced our characterization time by more than 60%.
-- Vinodh J Rakesh, Cypress Semiconductor Technologies
India Private Limited
author:
Vinodh J Rakesh -
Cypress Semiconductor Technologies India Private Limited
Tirumalesu Manda PRRK -
Cypress Semiconductor Technology India Private Limited
Jagadish Raju K -
Cypress Semiconductor Technologies India Private Limited
Jithesh PK -
Cypress Semiconductor Technologies India Private Limited
Cypress Semiconductor Corporation (NASDAQ: CY) is a leader in advanced embedded system solutions, providing solutions for the most innovative applications such as automotive, industrial, home automation, consumer electronics and medical products. Our Microcontroller and Connectivity Division (MCD) is mainly responsible for providing high-performance microcontroller units (MCUs), analog, wireless and wired connectivity solutions. Products include Traveo™ automotive MCUs, PSoC® programmable MCUs and general-purpose MCUs equipped with ARM® Cortex®-M4/M3/M0+/R4CPUs, analog PMIC power management ICs, CapSense® capacitive sensing controllers, TrueTouch® touch screens, Wi-Fi®, Bluetooth®, Bluetooth Low Energy and ZigBee® solutions.
In addition, it provides a range of USB controllers and solutions that comply with USB-C and USB Power Delivery (PD) standards. MCD achieved revenue of approximately US$1.4 billion in fiscal 2017 and serves many well-known automotive companies such as Continental, Denso, Visteon, Toyota and BMW.
Time-to-market pressures require faster chip characterization
Around 2011, due to time-to-market pressures and increasing customer demand in the mobile touchscreen market, Cypress adopted a new IP-based design approach that significantly shortened the product development cycle. This approach reduced the time spent on tapeout and reduced the number of bugs found in the First Silicon verification after tapeout. As a result, the speed and number of new product launches suddenly increased sharply. But the problem was that although the design team was able to design more products, the characterization team could not quickly characterize all products.
The characterization team at Cypress is responsible for testing the performance parameters of the entire PVT before mass production. On average, each product has about 400 performance parameters. To ensure that the product is suitable for mass production, we need to measure these 400 performance parameters one by one on 6-50 DUTs.
To meet customer schedule requirements, we must complete the entire process from chip provision to comprehensive product characterization within 4 to 8 weeks (depending on the complexity of the product). Otherwise, we will face the risk of delayed product release, which may lead to customer loss and millions of dollars in business losses. Our business goal is to occupy a leading position in the market, so improving Bench's characterization efficiency is urgent.
Improve the efficiency of characterization by increasing the parallelism, automation and standardization of the bench characterization system
The feature analysis team explored three approaches to achieve greater efficiency:
(1) increasing parallelism, (2) increasing automation, and (3) increasing code reuse and standardization.
Traditional bench characterization systems can only analyze one DUT at 50% automation, and the analysis capability is very limited, so we must use parallel characterization to improve efficiency. The
main idea of parallelism is to provide dedicated equipment for each DUT or at least use a sufficient number of equipment, and combine it with MUX (multiplexing) technology based on the switch matrix. In the end, we achieved an automation level of more than 90%.
If we want to characterize a typical PSoC, we need to measure current/voltage/timing on 64 digital pins and 4 power pins. To meet such test requirements, a single chip requires 68 measurement channels. Considering the requirement of 4x parallelism, we need a total of 272 measurement channels. The number of channels provided by traditional automated test equipment (ATE) in production workshops can meet this standard, but they often cannot meet the accuracy required for bench characterization. In addition, the cost of reproducing the ATE architecture in the bench is very high, and not all 68 pins need to be measured at the same time.
After a detailed study of all the previous test cases, we found that we need to measure up to 4 digital pins and 4 power pins at the same time. Considering the requirement of 4 times parallelism, we need to measure 32 pins at a time. Therefore, we only use 32 channels of high-precision SMU for time-sharing measurement to meet the requirements of our entire characteristic analysis system. These SMUs use a switch matrix layout. We use two NI PXIe-2532 (512 crosspoint) matrix switch modules to achieve time-sharing multiplexing of all 272 pins of the 4 DUTs to be tested. The LabVIEW-based characteristic analysis program will establish the necessary connections between the DUT pins and the SMU channels according to the test requirements when running. The architecture block diagram is shown in Figure 1.
Figure 1. Architecture of the characterization system
Despite the use of switch matrix-based multiplexing, the complete bench characterization system still requires an SMU with 32 channels. We ruled out traditional benchtop SMUs because they take up too much space and require additional wiring. We ultimately chose NI's PXI 4-channel SMU and combined 8 NI SMUs to meet the 32-channel test requirements.
Some products, such as the Traveo II automotive MCU, can also act as a master for multiple protocols, such as DDR HSSPI, Hyperbus, SPI, and SDHC. Therefore, the characterization process of these DUTs also involves source synchronous measurements. In synchronous measurements, the DUT (master) needs to provide a clock signal and synchronize the clock and exchange data with an external test instrument (slave). The measurement also includes shmoo analysis of the data with a resolution of about 100 picoseconds when the slave is protocol aware. However, traditional pattern generators, high-speed digital interfaces, and some ATEs do not respond well to external clocks. Moreover, general slave devices do not have the ability to shmoo clock-related data, and require the use of complex external discrete components (such as analog-to-digital signal converters) to ensure voltage compatibility between the master and slave devices, which can easily lead to system-level problems.
To avoid such problems caused by using actual slave devices, NI uses the NI PXI FlexRIO product family with programmable FPGAs to simulate slave device functions. FlexRIO devices can also implement programmable delays, with a resolution of about 40 picoseconds for fine delays and about 120 picoseconds for coarse delays. FlexRIO modules with analog front ends can implement the functions of analog-to-digital signal converters between DUT and slave devices. At the same time, NI's digital pattern instruments can also natively support Shmoo functions for rapid feature analysis (currently, NI recommends using PXIe-6570 and PXIe-6571 for timing and Shmoo analysis).
The transition from Single-Site characterization to Multi-site parallel characterization has brought us many benefits, and our engineering teams in Bangalore, Seattle, and Colorado quickly began to widely adopt this Multi-site platform. Previously, each center used different instrument systems and developed and maintained its own code base. This approach greatly limited code reuse, and sometimes it was difficult to reuse code between teams in different regions because automation programs, characterization boards, and instrument drivers were not standardized. Therefore, we had to quickly standardize the software layer of the system.
To solve this problem, Cypress and Soliton developed a framework based on the concept of object-oriented programming (LabVIEW OOP), which provides an abstraction layer on top of the device driver for building the entire feature analysis automation program. Different engineers can directly edit a single test project in an Excel spreadsheet to achieve seamless switching between instruments from different manufacturers without having to understand the specific instrument layer driver, which greatly speeds up development.
Figure 2. Transition from a benchtop system using six individual benchtop instruments to a standardized CyMatrix system using 34 instruments.
Improve the efficiency of feature analysis and bring higher benefits to the organization
4x parallelism has significantly reduced the time required for characterization, which allows us to identify and fix bugs faster. The new characterization system has directly reduced our characterization time by more than 60%. The characterization process for medium-complexity products now takes less than 4 weeks, compared to the previous 10 weeks. And the characterization time for high-complexity products has been reduced from 20 weeks or more to less than 8 weeks.
The number of employees in our characterization team has not changed much since 2011. Before automation, they could only characterize one or two products a year, but now they can characterize more than 5 products a year. Standardization and code reuse help us reduce the preparation work for new chips, avoid bugs, and improve the overall reliability of the characterization system. Although engineers and teams in different regions characterize products in different time zones, a bug reported in one bench can easily be reproduced somewhere else the next day. This is exactly how standardization helps our engineers improve productivity and they can spend more time on troubleshooting bugs instead of reproducing them.
Because we have achieved standardization and automation without sacrificing flexibility, we are now able to use the same framework for all debug activities. We have also removed all dedicated debug equipment and reused these instruments to build more characterization systems. In addition, we have adapted this characterization platform to help other teams characterize some test chips and memory products, which have very different architectures from SoC products.
"Standardizing the characterization workbench with CyMatrix helps development teams in different locations quickly reproduce problems found in the characterization center. This greatly shortens our debugging cycle and the time it takes to get our products to market," said Aaron E. Gordon, senior vice president of MCD at Cypress Semiconductor. He added, "We use standardized and automated equipment and settings to transfer characterization to a process similar to that of the manufacturing industry, while increasing parallelism to reduce analysis time, thereby greatly shortening the 'tapeout-sample-volume production' cycle."
“The CyMatrix platform allows Cypress to perform characterization in a standardized way with high parallelism,” said Bjarni Benjaminsson, director of product engineering at Cypress Semiconductor. “It is a fully automated characterization environment that plays a key role in reducing the overall development cycle of new products at Cypress. The automation of the platform also ensures that product characterization data is reproducible if the data needs to be revisited at a later stage.”
“The CyMatrix system has been a great addition to Cypress Colorado,” said Juan Rivera, electrical design engineer at Cypress Semiconductor Colorado. “It has not only improved the way we characterize new products, but has also significantly reduced cycle time.”
Inspired by the success of the MCD characterization platform, two other teams in other departments also built platforms with similar concepts, one team in India for characterization of high-performance clock sequencing products, and the other in Japan for characterization of PMIC products.
We are also sure that similar characterization systems will be deployed to other Cypress regional teams in the future driven by business needs. The significant advantages and high efficiency we have achieved in chip characterization are proof of this, which also means that all our efforts to achieve test procedure standardization and highly automated Multi-site parallel systems have paid off. We are also very confident in the scalability of this characterization platform and hope to apply it to wafer-level testing in the future.
Figure 3. Cypress Bangalore’s 4-site automated characterization system
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