[Evaluation of domestic FPGA Gaoyun GW1N-4 series development board]——4. Use of embedded logic analyzer
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This post was last edited by gs001588 on 2021-12-18 13:37
[Evaluation of domestic FPGA Gaoyun GW1N-4 series development board]——4. Use of embedded logic analyzer
——This post adds a test of the embedded logic analyzer based on the previous post (previous post: [Evaluation of domestic FPGA Gaoyun GW1N-4 series development board]——3. Light a lamp hello_led https://en.eeworld.com/bbs/thread-1189496-1-1.html)
Find the document folder in the Yunyuan software installation directory and refer to the document "SUG114-2.4_Gowin Online Logic Analyzer User Guide.pdf"
Create a new logic analyzer file GAO (Gowin Analyzer Oscilloscope), and the creation wizard will start after confirmation.
According to the wizard, press the default settings and click Next
The file name can be modified by yourself, usually the default is the project name
Creation completed
You can see that the file "hello_led.rao" is generated
Double-click the file "hello_led.rao" to set up triggering and capture.
First set the trigger, switch to the trigger options window "Trigger Options", double-click the trigger port "Trigger Port 0", the trigger port setting window pops up, which is empty, click the "plus sign" icon to add a trigger signal.
After clicking the "plus sign", a network search window pops up, click "Search" to search.
Search all the signals in the project, select only "COUNTER[25:0]", and confirm to add it.
You can see that the port setting window is no longer empty and the signal just added is already there. Confirm the settings.
In the matching unit setting window, check M0, double-click "NONE" in the trigger port setting to set the trigger port and set the trigger value.
Click the blank area in the "Expression" of the trigger expression window to pop up the expression setting. After selecting M0 to confirm, the expression window will have "M0" and will no longer be empty.
Switch to the Capture Selection Settings window and browse to add a sampling clock source.
Search and add "CLK_50M" as the sampling clock.
The sampling clock has been successfully set. Add capture semaphore, search for semaphore found.
Hold down the CTRL key, select the remaining three (or groups of) semaphores except "CLK_50M" in turn, and confirm the addition.
Capturing semaphore added successfully.
In the "Process" window, select synthesis or layout and routing, and select "Rerun All" in the right-click menu to completely recompile the project, which will add the logic analyzer function.
Launch the Logic Analyzer from the main toolbar
After starting the logic analyzer, check "Enable Programmer"
It is prompted that you need to download the configuration file for FPGA programming first. The "Fs File" file is different from the previous one and has been changed to ao_0.fs.
There are two .fs files in the project path. hello_led.fs is the configuration file without adding the logic analyzer, and ao_0.fs is the configuration file after adding the logic analyzer.
After successfully downloading the configuration file, the prompt turns green and is ready to run. Click the single execution icon (or press the shortcut key F1)
The data has been captured successfully, but is displayed in hexadecimal by default.
Select the signal, right-click the menu, follow the picture below, and select Unsigned Integer.
It is displayed as an integer for easy observation. However, the trigger edge is at the left and right, so it is inconvenient to see the previous state.
You can adjust the trigger position value to display the information before the trigger. You may change the position value from the default "0" to "10". Click Run again.
The captured signal shows the state before the trigger. The trigger scale just covers the LED transition edge, which is unacceptable for people with obsessive compulsive disorder. You may want to adjust the trigger value appropriately.
Change the trigger value from "25000000" to "25000002" and execute the capture again.
This time I can see it more clearly.
So far, the basic use of the embedded logic analyzer has been successful. There are still many advanced functions and other settings to be explored and gradually experienced in formal projects.
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