Design and implementation of various frequency division methods based on FPGA

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Design and implementation of various frequency division methods based on FPGA [Copy link]

Author: Gao Peijun, Institute of Modern Communications, Beijing Jiaotong University
This paper introduces the process of designing digital circuits using VHDL hardware description language input method, through the FPGA design and implementation of a general frequency divider that can realize equal duty cycle, unequal duty cycle integer frequency division and half-integer frequency division under the QuartursⅡ development platform.
Keywords : FPGA; VHDL hardware description language; digital circuit design; frequency divider

Introduction

Frequency divider is a basic circuit in digital system design. According to the needs of different designs, we will encounter even frequency division, odd frequency division, half-integer frequency division, etc. Sometimes equal duty cycle is required, and sometimes unequal duty cycle is required. In the same design, sometimes multiple forms of frequency division are required. Usually, various forms of even frequency division and odd frequency division with unequal duty cycle are formed by counters or cascades of counters, which are relatively simple to implement. However, it is more difficult to implement half-integer frequency division and odd frequency division with equal duty cycle. This paper uses VHDL hardware description language, QuartusⅡ3.0 development platform, and Altera's FPGA to design a more general frequency divider that can meet the above requirements.

1. Circuit Design

The following method can be used to implement a half-integer frequency divider using FPGA: design a modulo N counter, then design a pulse subtraction circuit, and deduct one pulse from every two pulses to implement a frequency divider with a division factor of N-0.5. The pulse subtraction circuit consists of an XOR gate and a 2-divider. Based on the principle of a half-integer frequency divider, this design adds an enable control signal to the XOR gate, and controls the XOR gate and the counter count state value to achieve multiple forms of frequency division in the same circuit, as shown in Figure 1.

2. Implementation of VHDL language

Now, by designing a frequency divider that can achieve 8.5 division, 17 division with equal duty cycle, 2, 4, 8, 16, 32 division, and 9 division with duty cycle of 1∶8 and 4∶5, the FPGA implementation of this universal frequency divider is introduced.

As shown in the circuit schematic diagram shown in Figure 1, the frequency divider consists of an XOR gate with an enable terminal, a modulo-N counter and a 2-divider. This design uses a D flip-flop to complete the 2-division function. The implementation method is: the Q inverted output terminal of the flip-flop is fed back to the input terminal D, and one of the counter's count output terminals is used as the clock input terminal of the D flip-flop. The VHDL language implementation of each functional module is as follows.

1. Implementation of Modulo N Counter

When using a counter in a general design, we can call the counter module in the lpm library, or we can use the VHDL language to design a modulo N counter ourselves. This design uses the VHDL language to design a counter with a maximum modulus of 16. The input ports are: enable signal en, reset signal clr and clock signal clk; the output ports are: qa, qb, qc, qd. Its VHDL language description is omitted.

2. The input of the XOR gate with enable control
is: xor_en: XOR enable, a and b: XOR input; the output is: c: XOR output. When xor_en is high, c outputs the XOR value of a and b. When xor_en is low, c outputs signal b. Its VHDL language is omitted.

3.2 The implementation of frequency division (flip-flop)
has the following inputs: clock signal clk, input signal d; outputs: q: output signal a, q1: output signal a inverse. The VHDL language is omitted.

4. Implementation of the frequency divider
This design adopts a hierarchical design method. First, the components of the frequency divider circuit are designed and implemented. Then, through the method of component instantiation, each component is called to implement the entire frequency divider. The VHDL language is omitted.

3. Simulation results and hardware circuit testing

The purpose of this design is versatility and simplicity. Various forms of frequency division can be achieved by slightly modifying the above program.

1. Achieve 8.5-frequency division and 17-frequency division with equal duty cycle

As long as the ports qa, qb, and qc are matched to the open state when calling the counter module in the above program, and xor_en is set to a high level, it can be done. From the compilation report, it can be seen that a total of 8 logic elements are occupied, and the simulation waveforms are shown in Figures 2 to 4

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Figure 2

Figure 3

Figure 4 From the waveforms of qxiao and clk, we can see that every 8.5 clock cycles, the qxiao signal generates a rising edge, thus achieving a frequency division factor of 8.5, and at the same time, a frequency division of 17 with equal duty cycle is obtained at the qzheng end. If clk is 170MHz, the qxiao output is 20MHz and the qzheng output is 10MHz.

2. Realize the duty ratio of 1:8 and 4:5 with 9-frequency division

As long as the xor_en in the above program is set to low level, a 9-frequency division signal with a duty cycle of 1:8 can be output at qxiao; and a 9-frequency division signal with a duty cycle of 4:5 can be output at qzheng2. It also only occupies 8 logic elements. The simulation waveform is as follows.

3. To achieve 2, 4, 8, 16 and 32 frequency divisions with equal duty cycles
, just set xor_en in the above program to low level and set the maximum count value of the counter module to 16. The simulation waveform is as follows.

It can be seen that as long as the count state value of the counter is slightly changed and the XOR gate is gated, the above-mentioned various forms of frequency division can be achieved. This design has been tested on the test platform composed of Altera's EP1K50QC208-3 and has good performance.

Conclusion

We used the above-mentioned various forms of frequency division when designing simulated radar pulse signals and developing spread spectrum chips with FPGA. This article aims to introduce a method for implementing multiple frequency divisions required for FPGA development. If the design requires more frequency division forms, you can directly use this design and slightly modify the program to meet your own design requirements. If the design requires fewer frequency division forms, you can use part of the program of this design to save resources.

References

1 Xu Zhijun, Xu Guanghui. Development and Application of CPLD/FPGA, Electronic Industry Press
2 Hou Boheng, Gu Xin. VHDL Hardware Description Language and Digital Logic Circuit Design, Xidian University Press
3 ALTERA Company, Introduction to QuartusⅡ

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Very detailed, very good and clear