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Master guide fpga altera to divide the 50MHZ clock to read rom data, mif file [Copy link]

 This post was last edited by Thomas520 on 2018-11-28 10:12 Attached is the MIF file. And the generated rom image


QQ截图20181128101149.png (9.01 KB, downloads: 0)

QQ截图20181128101149.png

FPGA.png (6 KB, downloads: 0)

FPGA.png

QQ截图20181128101336.png (15.9 KB, downloads: 0)

QQ截图20181128101336.png

SpwmRom1.mif

2.63 KB, downloads: 1

This post is from Altera SoC

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Little Meige's  Details Published on 2018-11-28 11:50
 
 

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There is such a document in the forum, you can find it yourself. As for how many 50M frequency divisions you have, you did not say. In addition, you can find a book to learn how to write the frequency divider.
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heningbo posted on 2018-11-28 08:45 There is such a document in the forum, look for it yourself. As for how many 50M frequency divisions you did not say. In addition, find a book to learn how to write the frequency divider
I don't know which one it is, I searched for rom and so on but didn't find it
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