Design Example of Half-Integer Frequency Divider Based on CPLD/FPGA

1 Introduction

CPLD (Complex programmable logic device) and FPGA (Field programmable gate array) are both programmable logic devices, which are developed on the basis of PAL, GAL and other logic devices. Compared with the previous PAL and GAL, FPGA/CPLD is larger in scale and suitable for the application of sequential, combinational and other logic circuits. It can replace dozens or even hundreds of general-purpose IC chips. This chip has the characteristics of being programmable and easy to change the implementation scheme. Since the description of the hardware connection relationship inside the chip can be stored in a disk, ROM, PROM, or EPROM, a new function can be realized by replacing an EPROM chip while the programmable gate array chip and peripheral circuits remain unchanged. It has the advantages of short design and development cycle, low design and manufacturing cost, advanced development tools, no need to test standard products, stable quality and real-time inspection, so it can be widely used in product principle design and product production. FPGA and CPLD devices can be applied to almost all occasions where gate arrays, PLDs and small and medium-sized general-purpose digital integrated circuits are used.

In modern electronic systems, digital systems account for an increasing proportion. The trend of system development is digitalization and integration, and CPLD/FPGA, as a programmable ASIC (application-specific integrated circuit) device, will play an increasingly important role in digital logic systems.

In digital logic circuit design, the frequency divider is a basic circuit. It is usually used to divide a given frequency to obtain the required frequency. The implementation of the integer frequency divider is very simple. It can be implemented using a standard counter or a programmable logic device. However, in some cases, the clock source is not an integer multiple of the required frequency. In this case, a fractional frequency divider can be used for frequency division. For example: a half-integer frequency divider with a frequency division coefficient of 2.5, 3.5, 7.5, etc. When simulating the design of the frequency meter pulse signal, the author used a circuit such as a half-integer frequency divider. Since the clock source signal is 50MHz, and the circuit needs to generate a 20MHz clock signal with a division ratio of 2.5, integer frequency division will not be able to do the job. In order to solve this problem, the author used the VIDL hardware description language and schematic input method, and conveniently completed the design of the half-integer frequency divider circuit through MAX+plusII development software and ALTERA's FLEX series EPF10K10LC84-4 FPGA.

2 Basic principles of fractional frequency division

The basic principle of fractional frequency division is to use pulse throughput counter and phase-locked loop technology to first design two integer frequency dividers with different frequency division ratios, and then obtain the required fractional frequency division value by controlling the different number of times the two frequency division ratios appear in a unit time. For example, when designing a frequency divider with a frequency division coefficient of 10.1, the frequency divider can be designed to be 9 times 10 division and 1 time 11 division, so the total frequency division value is:

F=(9×10+1×11)/(9+1)=10.1

From the characteristics of this implementation method, it can be seen that the signal jitter obtained after frequency division is large because the frequency division value of the frequency divider is constantly changing. When the frequency division coefficient is N-0.5 (N is an integer), the time of deducting the pulse can be controlled to make the output a stable pulse frequency, rather than N division once and N-1 division once.

Figure 2 Modulo 3 counter simulation waveform

3 Circuit composition

The divider circuit with a division factor of N-0.5 can be composed of an XOR gate, a modulo-N counter and a divider by two. When implementing, the modulo-N counter can be designed as a counter with a preset, so that any divider with a division factor of N-0.5 can be realized. Figure 1 shows the circuit composition of a general half-integer divider.
Using the VHDL hardware description language, any modulo-N counter (whose operating frequency can reach more than 160MHz) can be realized, and a modulo-N logic circuit can be generated. After that, the modulo-N logic circuit, the XOR gate and the D flip-flop are connected using the schematic input method to realize a half-integer (N-0.5) divider and a (2N-1) divider. [page]

4 Half-integer divider design

This paper presents a general method of designing a half-integer frequency divider using FPGA by designing a frequency divider with a division factor of 2.5. The 2.5 frequency divider consists of a modulo 3 counter, an XOR gate and a D flip-flop.

Figure 3 2.5 divider circuit schematic

4.1 Modulo 3 Counter

This counter can generate a frequency divider with a frequency division factor of 3 and generate a default logic symbol COUNTER3. Its input ports are RESET, EN and CLK; its output ports are QA and QB. The following is the VHDL description code of the modulo 3 counter:

The description structure of the arbitrary modulus counter is exactly the same as that of the modulo 3 counter, the only difference is the number of states of the counter. After the above program is compiled and time-series simulated, the simulation waveform shown in Figure 2 can be obtained in MAX+PLUSII. [page]

4.2 Complete circuit and waveform simulation

COUNTER3, XOR gate and D flip-flop are connected through the circuit logic relationship shown in Figure 3, and are imported into the graphic editor using the schematic input method. Then, the simulation waveform shown in Figure 4 can be obtained through logic synthesis. From the waveforms of outclk and inclk in the figure, it can be seen that outclk will generate a rising edge every 2.5 cycles of inclk, thereby realizing a frequency divider with a division factor of 2.5. If inclk is 50MHz, then outclk is 20MHz. Therefore, it can be seen that this circuit can not only obtain a frequency divider with a division factor of 2.5 (outclk), but also a frequency divider with a division factor of 5 (Q1).

5 Conclusion

After using ALTERA's FLEX series EPF10K10LC84-4 FPGA device to implement half-integer frequency division, the adaptation analysis results after logic synthesis are listed in Table 1. The counter in this example is a 2-bit wide bit vector, that is, the frequency division coefficient is a half-integer value within 4. If the frequency division coefficient is greater than 4, the bit width of count needs to be increased.

Table 1 Half-integer divider adaptation analysis results