Choose VHDL or Verilog HDL

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Choose VHDL or Verilog HDL [Copy link]

Hardware Description Language HDL (Hardware Describe Language)


HDL Overview

With the development of EDA technology, it has become a trend to design PLD/FPGA using hardware language. The most important hardware description languages are VHDL and Verilog HDL. VHDL was developed earlier and has strict syntax, while Verilog HDL is a hardware description language developed on the basis of C language with a more free syntax. Compared with VHDL and Verilog HDL, the writing rules of VHDL are more complicated than Verilog, but the free syntax of Verilog also makes it easy for a few beginners to make mistakes. Many foreign electronic majors will teach VHDL at the undergraduate level and Verilog at the graduate level. From a domestic perspective, there are many reference books on VHDL, which is convenient for finding information, while there are relatively few reference books on Verilog HDL, which brings some difficulties to learning Verilog HDL. From the perspective of the development of EDA technology, hardware C language compiler software for CPLD/FPGA design has appeared. Although it is still immature and rarely used, it may become another means of designing large-scale CPLD/FPGA after VHDL and Verilog.



Choose VHDL or Verilog HDL?

This is the most common question for beginners. In fact, the difference between the two languages is not big, and their descriptive capabilities are similar. After mastering one of the languages, you can learn the other language faster through short-term learning. The choice of language mainly depends on the usage habits of the people around you, so that it will be convenient for future learning and communication. Of course, if you are an integrated circuit (ASIC) designer, you must first master Verilog, because in the field of IC design, more than 90% of companies use Verilog for IC design. For PLD/FPGA designers, the two languages can be freely chosen.



Several important tips for learning HDL

1. Understand the synthesizability of HDL:

HDL has two uses: system simulation and hardware implementation. If the program is only used for simulation, then almost all syntax and programming methods can be used. But if our program is used for hardware implementation (for example: for FPGA design), then we must ensure that the program is "synthesizable" (the program's functions can be implemented with hardware circuits). Non-synthesizable HDL statements will be ignored or reported errors during software synthesis. We should keep in mind that "all HDL descriptions can be used for simulation, but not all HDL descriptions can be implemented with hardware."

2. Use hardware circuit design ideas to write HDL:

The key to learning HDL well is to fully understand the relationship between HDL statements and hardware circuits. Writing HDL is to describe a circuit. After writing a program, we should have a general understanding of the generated circuit, and we cannot use pure software design ideas to write hardware description language. To do this, we need more practice, more thinking, and more summarization.

3. Grammar mastery is more important than

30% of basic HDL statements to complete more than 95% of circuit design. Many uncommon statements cannot be supported by all integrated software. When the program is transplanted or the software platform is changed, it is easy to cause compatibility problems, and it is not conducive to others to read and modify. It is recommended to study common statements carefully and understand the hardware meaning of these statements. This is much more useful than mastering a few new syntaxes.



The relationship between HDL and schematic input method

The relationship between HDL and traditional schematic input method is like the relationship between high-level language and assembly language. HDL has good portability and is easy to use, but it is not as efficient as schematics; schematic input has good controllability, high efficiency, and is relatively intuitive, but it is cumbersome and has poor portability when designing large-scale CPLD/FPGA. In real PLD/FPGA design, it is usually recommended to use a combination of schematics and HDL to design. Schematics should be used where schematics are suitable, and HDL should be used where HDL is suitable. There is no mandatory rule. Our ultimate goal is to design an efficient, stable circuit that meets the design requirements in the shortest time using the tools we are most familiar with. The complete process of developing PLD/FPGA using VHDL/VerilogHD language in



HDL development process is as follows: 1. Text editing: It can be done with any text editor, or a dedicated HDL editing environment. Usually VHDL files are saved as .vhd files, and Verilog files are saved as .v files. 2. Functional simulation: Import the file into HDL simulation software for functional simulation to check whether the logic function is correct (also called pre-simulation. For simple designs, this step can be skipped and timing simulation is performed only after the wiring is completed). 3. Logic synthesis: Import the source file into the logic synthesis software for synthesis, that is, synthesize the language into the simplest Boolean expression and signal connection relationship. The logic synthesis software will generate an .edf (edif) EDA industry standard file. 4. Layout and routing: Import the .edf file into the software provided by the PLD manufacturer for wiring, that is, place the designed logic into the PLD/FPGA. 5. Timing simulation: It is necessary to use the precise parameters obtained in the layout and routing to verify the timing of the circuit with the simulation software. (Also called post-simulation) 6. Programming download: After confirming that the simulation is correct, download the file to the chip. Usually the above process can be completed in the development tools provided by PLD/FPGA manufacturers (such as MAXPLUSII, Foundation, ISE), but many integrated PLD development software only supports a subset of VHDL/Verilog, which may cause a few syntaxes to fail to compile. If a dedicated HDL tool is used to execute separately, the effect will be better. Otherwise, there will be no reason for so many companies selling dedicated HDL development tools to exist.

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Learning Verilog not only requires learning the syntax rules of the hardware language, but also learning how to use it for modeling, simulation, and synthesis, starting with the basic language structure, data flow, behavioral modeling, and more advanced learning of bipolar and multi-level logic optimization, timing analysis and optimization, RTL synthesis, and yes, simulation, etc. It seems difficult to improve by reading books on your own. You need to put in some effort to study, and it would be best if someone could give you some pointers and cooperate with you in doing some exercises. If you really want to learn, there won't be any big problems.

houdazhi

Which book is better for learning Verilog HDL? I just started learning

settleinsh

Xia Yuwen's book is a classic

settleinsh

I forgot to tell you the name, "Verilog Digital System Design Tutorial", almost everyone has a copy

hbtm_wangjin

I support!

bluecat600

Verilog Digital System Design Tutorial by Xia Yuwen from Beihang University

antandtree

I just want to learn. Thank you

wwwocean

After finishing, let's see

shuibeizi

VHDL is suitable for beginners and is easy to communicate with others.

何其狂

Choose carefully

HDLWorld

VHDL was born out of the US military standard and first became the IEEE specification. Verilog came from Cadence's contribution. Since VHDL became a specification earlier than Verilog, the earliest designers all adopted VHDL. Later, Verilog also became the IEEE standard, and both languages were widely adopted. Since Verilog is better supported by EDA manufacturers, it has developed faster. Currently, the strongest SystemVerilog has been developed as an extension of Verilog, while VHDL has basically stagnated. Therefore, from a prospective perspective, VHDL will inevitably be replaced by Verilog. From the perspective of design characteristics, the same design can be described in Verilog with half the number of lines of code than VHDL. At the same time, the simulation speed of Verilog is faster than that of VHDL. In fact, the development trend is still in the hands of EDA tool developers. The development direction of EDA tools will play a decisive role in the development of design languages.

coder001

Take a look at everyone's replies, learn from everyone's spirit, and benefit a lot! !

coder001

You are so right. It would be great if we were no longer controlled by others.