Choose VHDL or Verilog HDL or System Verilog?

Hardware Description Language HDL (Hardware Describe Language)

HDL Overview

With the development of EDA technology, it has become a trend to design PLD/FPGA using hardware language. The main hardware description languages ​​at present are VHDL, Verilog HDL and System Verilog. VHDL was developed earlier and has strict syntax; Verilog HDL is a hardware description language developed on the basis of C language, with a more flexible syntax; System Verilog can be regarded as an upgraded version of Verilog HDL, which is closer to C language and supports multi-dimensional arrays. Compared with VHDL and Verilog HDL, VHDL has very strict writing rules and syntax requirements. For example, different data types are not allowed to be assigned to each other but need to be converted. Irregular codes written by beginners will generally report errors when compiled; Verilog is more flexible, and the results of the synthesis may not be what the programmer wants at some point. Since there is not much information about System Verilog, few people currently understand it. According to a survey, there are more companies using Verilog HDL than using VHDL in China. From the perspective of EDA technology development, hardware C language compiler software for CPLD/FPGA design has appeared. Although it is not mature yet and has very few applications, it may become another means of designing large-scale CPLD/FPGA after VHDL and Verilog.


Choose VHDL, Verilog HDL or System Verilog?

This is the most common question for beginners. In fact, the difference between these three languages ​​is not big, and their description capabilities are similar. After mastering one of the languages, you can learn another language quickly through short-term learning. It is even easier to learn System Verilog after mastering Verilog HDL. The choice of language mainly depends on the usage habits of the people around you, which can facilitate future learning and communication. Of course, if you are an integrated circuit (ASIC) designer, you must first master Verilog, because in the field of IC design, more than 90% of companies use Verilog for IC design. For PLD/FPGA designers, the three languages ​​can be freely selected. If you are familiar with C language, it is recommended that you learn Verilog HDL. You will find that many syntax and keywords of Verilog HDL are the same as those in C language, so that you can quickly break through the language barrier and get started quickly.


Several important tips for learning HDL

1. Understand the problem of HDL synthesizability:

HDL has two uses: system simulation and hardware implementation. If the program is only used for simulation, then almost all syntax and programming methods can be used. But if our program is used for hardware implementation (for example: for FPGA design), then we must ensure that the program is "synthesizable" (the program's functions can be implemented with hardware circuits). Non-synthesizable HDL statements will be ignored or reported errors during software synthesis. We should keep in mind that "all HDL descriptions can be used for simulation, but not all HDL descriptions can be implemented with hardware." 2. Use hardware circuit design ideas to write HDL: The key to learning HDL well is to fully understand the relationship between HDL statements and hardware circuits. Writing HDL is to describe a circuit. After we write a program, we should have a general understanding of the generated circuit, and we cannot use pure software design ideas to write hardware description language. To achieve this, we need more practice, more thinking, and more summary. 3. Grammar mastery is more important than precision. More than 20% of basic HDL statements can complete more than 80% of circuit design, and 30% of basic HDL statements can complete more than 95% of circuit design. Many uncommon statements are not supported by all integrated software. When the program is transplanted or the software platform is changed, it is easy to cause compatibility problems, and it is not conducive to reading and modifying by others. It is recommended to study common statements carefully and understand the hardware meaning of these statements. This is more useful than mastering a few new syntaxes. The relationship between HDL and schematic input method The relationship between HDL and traditional schematic input method is like the relationship between high-level language and assembly language. HDL has good portability and is easy to use, but it is not as efficient as schematics; schematic input has good controllability, high efficiency, and is more intuitive, but it is very cumbersome and poorly portable when designing large-scale CPLD/FPGA. In real PLD/FPGA design, it is usually recommended to use a combination of schematics and HDL to design. Use schematics where it is suitable for schematics, and use HDL where it is suitable for HDL. There is no mandatory regulation. Our ultimate goal is to design an efficient, stable circuit that meets the design requirements in the shortest time using the tools we are most familiar with. HDL development process The complete process of developing PLD/FPGA using VHDL/VerilogHD language is as follows: 1. Text editing: It can be done with any text editor, or with a dedicated HDL editing environment. Usually VHDL files are saved as .vhd files, and Verilog files are saved as .v files. 2. Functional simulation: Import the file into the HDL simulation software for functional simulation to check whether the logic function is correct (also called pre-simulation, this step can be skipped for simple designs, and only timing simulation is performed after the wiring is completed) 3. Logic synthesis: Import the source file into the logic synthesis software for synthesis, that is, synthesize the language into the simplest Boolean expression and signal connection relationship. The logic synthesis software will generate the EDA industry standard file of .edf (edif). 4. Layout and routing: transfer the .edf file into the software provided by the PLD manufacturer for routing, that is, place the designed logic into the PLD/FPGA 5. Timing simulation: the precise parameters obtained in the layout and routing need to be used to verify the timing of the circuit with simulation software. (Also called post-simulation) 6. Programming download: after confirming that the simulation is correct, download the file to the chip Usually, the above process can be completed in the development tools provided by the PLD/FPGA manufacturer (such as QuartusII, ISP, ISE), but many integrated PLD development software only supports a subset of VHDL/Verilog, which may cause a few syntaxes to fail to compile. If a dedicated HDL tool is used to execute separately, the effect will be better, otherwise there will be no reason for so many companies selling dedicated HDL development tools to exist.