FPGA PLL Loss of Lock

ranming

FPGA PLL Loss of Lock [Copy link]

I made two cyclone4 EP4CE6E22C8 boards, and after soldering them, I found that other functions were fine, but the PLL output frequency was wrong.

50M crystal input, 5M, 50M, 100M, 200M output. The measured output is about one thousandth of the output frequency, and the frequency is slightly different each time it is powered on.

The phenomenon is the same on both boards. The crystal input clock is divided by 100,000,000 and given to the indicator light at a frequency of 0.5Hz. There seems to be no problem.

Anyone knows what the reason is?

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