Four memory protection issues of TI C66x DSP

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Four memory protection issues of TI C66x DSP [Copy link]

1. Memory protection issues when the CPU accesses external memory (DDR3 or MSM);

2. Memory protection issues when peripherals (such as SRIO, QM, FFTC, etc.) access external memory;

3. The memory protection problem when the CPU accesses the internal resources (L1, L2 memory) of its own corePac is implemented by the respective memory controller;

4. Memory protection issues when peripherals (such as SRIO, QM, FFTC, etc.) access corePac internal resources (L1, L2 memory);

The purpose of memory protection is to make each CPU only access the memory allocated to it (such as L1, L2, MSM, DDR. This is achieved by setting access permissions). Once the memory that does not belong to it and that it has no permission to access is accessed (caused by errors in code logic, etc.), an exception will be reported (triggered by the corresponding event), causing the DSP to crash. This is conducive to investigating the problem and finding the root cause.

The implementation mechanisms of the four memory protections are different, which will be described in detail in other blogs.