TI C66x four memory protection issues

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TI C66x four memory protection issues [Copy link]

This problem has been encountered in code maintenance. The CPU accessed the address 0x75510C55 of the external memory space of corePac, that is, the CPU initiated access to the memory to the L2 memory controller of corePac, and then the L2 memory controller sent the request to the XMC module of corePac. The XMC module checked whether the address was legal based on the configured registers (i.e., the mapping of 32-bit virtual address to 36-bit physical address and memory permission registers. Each memory segment of 16M is set with a register, and each CPU has the same multiple such registers). It was found that the address was not set in any of these registers, that is, the XMC regarded the memory as an illegal address. Then the illegal address access will be reported through the L2 memory controller. The L2 memory controller reports the error through system event 0x6E = 110 (event 110 and this type of illegal memory access MDMAError mapping are fixed. Refer to corePac user guide section 9.3 ). The user can do something of his own in the exception handling function registered to event 110 (such as actively crashing other CPUs of the DSP, etc., so that the entire DSP stops working, which saves the scene and facilitates the investigation of the problem). The system will set the MDMAError register and display the error type to the user in the register. As shown in the figure, MDMAErr = 0x400003 02 , LSB 0x02 means privilege error, that is, the CPU has no permission to access the address 0x75510C55.

The above-mentioned checking mechanism is implemented by hardware.

The following explains the memory address 0x75510C55 when the CPU wants to access the corePac external memory. The access initiated by the CPU is a 32-bit virtual address. Therefore, in order to actually access the physical address of the external memory (such as DDR), it must be mapped to a 36-bit physical address by the XMC module mentioned above. The 0x75510C55 here is the 32-bit virtual address initiated by the CPU, and the XMC will detect that the address is illegal. At the same time, it can be seen from the last figure (see TI C66x data manual table 2-2 Memory Map Summary. In fact, this address is reserved, that is, the CPU and any peripherals cannot access the reserved address, and users cannot map these reserved addresses to physical addresses. When the CPU accesses these reserved addresses, the above error will be reported.

So here the user does not map the address 0x75510C55 in the XMC register . Of course, the XMC will think it is an illegal address when detecting it.