Implementation of Digital Audio Broadcast Channel Encoder Based on FPGA

1 Digital Audio Broadcasting (DAB) Transmission System and Channel Encoder

DAB is the third generation broadcasting system after AM and FM broadcasting. Compared with analog broadcasting, it can not only provide high-quality sound signals (CD quality), but also provide data, images and other additional services. It can guarantee the sound quality during high-speed mobile reception and has strong anti-interference ability. In the same bandwidth and environment, DAB can provide high-quality and diverse radio programs.

The DAB transmission system mainly includes the source encoder at the program provider, the multiplexer at the broadcasting station studio and the COFDM (Coded Orthogonal Frequency Division Multiplexing) coding modulator inside the transmitter. COFDM can be divided into channel coding, OFDM modulation and digital up-conversion. This article mainly discusses the use of FLEX10K series FPGA to implement the channel coding function.

The channel coding part of DAB mainly includes energy diffusion, convolutional coding and deletion, time interleaving, etc. The input is the ETI (Ensemble Transport InteRFace) frame from the multiplexer, and the output is the DAB transmission frame. The role of energy diffusion is to diffuse the spectrum by randomizing the binary sequence, reducing the occurrence of consecutive '0' and consecutive '1', so as to ensure that the bits at the receiving end are restored on time. For signal transmission, since convolutional coding introduces a large number of redundant bits, the channel coding of DAB adopts deletion-type convolutional coding. The DAB transmitter uses time interleaving technology to correct sudden block errors. It disrupts the order of data arrangement according to established rules, so that the block errors in the channel are scattered in different frames. Combined with the point error correction capability of convolutional coding, the receiver can correct the block errors that often occur in mobile transmission.

2 FLEX10K Series Features

The FLEX10K series is an embedded programmable logic device (PLD) produced by Altera. The Flex changeable logic cell array uses reconfigurable CMOS SRAM cells, and its structure integrates all the features required to realize a general-purpose multifunctional gate array. The FLEX10K series device has a capacity of up to 250,000 gates and can integrate the entire digital system into a single device with high speed and high performance. The high density of the FLEX10K series and the ease of implementing complex macro functions and memory in the design make it adaptable to the requirements of system-level design.

FLEX10K devices can be developed through Altera's MAX PLUS II system, which has powerful functions and supports multiple input methods such as schematics, hardware description languages ​​(VHDL, AHDL, VerilogHDL), etc. Using FPGA to implement DAB channel encoders greatly simplifies the system structure. In addition, the use of VHDL description language shortens the development time, enhances the readability of the system, and facilitates the upgrade of subsequent products. If you want to change the software design, you only need to modify the program, recompile, and download it, which is very convenient. Even if you want to change the hardware design, you can also achieve it by reallocating FPGA pins without large-scale changes to the original hardware. From the functional characteristics of the channel encoder, most of them are bit operations. If DSP or single-chip microcomputer is used, each instruction cycle can only process one bit in a byte, which is quite inefficient. FPGA can operate on multiple bits in parallel at the same time, greatly improving the processing efficiency. Since the highest operating frequency of FPGA is above 100MHz, the speed of data processing can be increased by increasing the operating frequency of FPGA.

The FLEX10K100A FPGA used in this design is one of the FLEX10K series. It has an equivalent gate count of 100,000 gates, built-in 24K bytes of RAM, 189 available I/O pins, a core voltage of 3.3V, and supports 5V input and output. The design adopts a mixed input method of schematic diagram and VHDL language.

3. Implementing channel coding function with FPGA

DAB channel coding technology includes ETI demultiplexing, energy diffusion, convolutional coding and deletion, and time interleaving. ETI demultiplexing and system control are implemented by a DSP ADSP2181, and the core parts of energy diffusion, convolutional coding, deletion and time interleaving are all implemented by a FLEX10K100A. An ETI frame mainly includes frame header information, relevant information of the frame and each sub-channel in the frame, and main service flow data MST including audio data code stream and fast data channel (FIC). Figure 1 is a schematic diagram of the hardware implementation of channel coding.

The code stream (ETI) from the multiplexer passes through the E1 interface board, and the ETI frame is decoded and stored in the input dual-port RAM buffer. At the beginning of each frame (24ms), the controller 2181 reads the ETI frame from the input buffer and calculates a set of control vectors based on the frame header information, writes it back to the input buffer, and then starts the FPGA. The FPGA first reads the control vector, and then reads the sub-channel data of the MST domain in the ETI frame according to its description and performs energy diffusion, convolution coding and deletion, and time interleaving. The result is output to the output buffer to the OFDM modulator. The SRAM interleaving buffer is used to store the 6 frames of data used for interleaving. [page]

The controller of channel coding is implemented by adsp2181, which controls all actions of the entire channel coding process, including starting the coding module FPGA to start coding, controlling FPGA to read data from the corresponding address of the external memory, providing the coding module with all the parameters required for convolution coding, and providing storage addresses for the encoded data.

The following is a detailed description of the process of implementing channel coding using FPGA. After DSP calculates the control information, it starts FPGA. FPGA first reads the first few frame feature bytes of the calculated control vector, determines the number of sub-channels including the FIC channel and the starting address of the input data based on these bytes, then reads the feature bytes of each sub-channel respectively, and processes each sub-channel according to its description.

3.1 Energy Diffusion

Energy diffusion is implemented by 9 D flip-flops and logic gates using the schematic input method. In the FPGA, data is first read in byte by byte, and then parallel/serial conversion is performed. The serial input code stream is modulo-2 added with the pseudo-random bit sequence (PRBS) with the generating polynomial Px=x9+x5+1 and the initial state is all '1'. The order of the processing is the XOR of the 0th bit of the serial input and the 0th bit of the PRBS sequence, and the output code stream of energy diffusion is obtained. The output serial code stream is sent to the convolution encoder. Figure 2 is the implementation principle diagram of energy diffusion.

3.2 Convolutional Coding

The convolution encoder also uses the schematic input method, as shown in Figure 3, and is implemented by a combination of shift registers and their different taps. [/td][/tr][tr][td=2,1] The initialization state of the register is all '0', and each input bit will produce 4 bits of output. When the valid data is sent, 6 more '0's must be sent to clear all registers. If the input sequence is of length I, the output sequence is. The output sequence can also be expressed as U = (u0 u1 u2…u4i+23 where ui = x (i = 0, 1, 2, ..., 4I+23), where R and Q are the remainder and quotient of i/4 respectively.

3.3 Deletion of Convolutional Coding

The first 4I bits of the convolutional coding output are divided into continuous bit blocks, each block has 128 bits. Each block is further divided into 4 sub-blocks of 32 bits. These 4 sub-blocks use the same deletion mode, which is determined by PI. Table 1 is a part of the deletion mode table. The output of the convolutional coding is ANDed with the deletion vector V in the deletion mode table, and the remaining bits are pushed into a stack. When the number of bits accumulated in the 16-bit stack is greater than 8, the encoder outputs the deletion result by byte to the interleaving buffer of 16 frames for temporary storage. The reading of the original data, energy diffusion, convolutional coding and deletion are carried out simultaneously. When the data of a sub-channel (or FIC) is read, the energy diffusion also stops at the same time, but the coding and deletion do not stop. The last 24 bits must be coded and deleted. These 24 bits are deleted using a fixed deletion vector VT = (1100 1100 1100 1100 1100 1100). For those with padding bytes (Pad), padding must be added, and finally a byte is output.

PI is determined by the bit rate of the input code stream, the protection level (P) and the protection mode (EEP/UEP). In UEP (unbalanced error protection), the code stream of the entire frame (a sub-channel) is divided into 3 or 4 blocks (L1~L4), and then the PI and the number of padding bits of the corresponding block are obtained by looking up the table. Table 2 is a part of this protection level mode table. For EEP (balanced error protection), there are two types of protection mode tables, A and B, corresponding to the input code rate is an integer multiple of 8Kbits/s and an integer multiple of 32Kbits/s, respectively, and a sub-channel in each frame is divided into 2 blocks. The general deletion process is performed by looking up the table, and the table lookup work here is completed by the controller, and the table lookup result is stored in the control vector byte. FPGA can directly encode according to the result, effectively reducing the complexity of FPGA.

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3.4 Time Interleaving

When interleaving starts, the FPGA has written the results of convolutional coding deletion sequentially into the interleaving buffer, and then reads out the data in random order according to the interleaving rules to complete the time interleaving with an interleaving depth of 16 frames. This buffer is a 128K-byte SRAM, divided into 16 8K blocks, each of which is used to store the convolutional coding results of one frame. The address organization of the SRAM is shown in Figure 4 (the starting address of each frame is in brackets).

The interleaving rules shown in Table 3 correspond to a 128K interleaving buffer, where r is the sequence number of the input frame, r' is the sequence number of the output frame, i represents the sequence number of the bit, R(i/16) represents the remainder of i divided by 16, and r\'(ri) represents that the i-th bit of the output r\'th frame should correspond to the i-th bit of the output r-th frame. Ram_addr represents the starting address of this frame in the interleaving buffer.

In order to meet the symbol format required by the lower-level OFDM modulator of the DAB transmission system, the interleaved result must be written into the output dual-port RAM buffer in bytes to meet the data structure of the transmission frame. According to the requirements of the DAB transmission frame, the output buffer here can accommodate data of 4 logical frames, and its chip selection logic also changes every 96ms. The data structure in the output RAM buffer is shown in Figure 5.

As mentioned above, the DAB channel encoder can be fully implemented by a single FLEX10K series FPGA (aDSP2181 as the controller). This method is easy to implement, stable, fast, and easy to upgrade, and can serve as the core technology foundation for the development of integrated dedicated ASIC chips in the future.