Design of USB Interface for Embedded System Based on FPGA

Design an FPGA -based IP-BX telephone application system for the interface connection between the traditional telephone network (PSTN) and the PC . The USB2.0 interface device EZ-USB FX2 CY7C68013A-56 works in slave FIFO mode, providing data and command channels between the FPGA - based embedded system and the PC, thereby meeting the high-speed transmission of data and commands between the PC and FPGA, and realizing telephone communication between the PSTN and the PC. The hardware debugging results show that the system works stably and the call quality meets the requirements.

Keywords: interface; FPGA; USB2.0; slave FIFO

Universal Serial Bus (USB) is an interface technology used in the PC field and has been widely used. USB2.0 has become the standard expansion interface in current computers. The purpose of this system design is to provide a digital interface between the public switched telephone network (PSTN) and the PC. In the design, the PC is the host and the FPGA-based embedded system is the USB device. This system is a simplified system of IP-PBX. A lot of work is done by the PC server. Here we focus on the USB interface design with FPGA as the control core.

1 System structure design

The system realizes free and efficient communication between PSTN network and Internet network through TRM (Telephone Response Module) and PC server. Figure 1 is a schematic diagram of the whole system structure.

System working process: When there is an incoming call, DAA requests an interrupt from FPGA. After receiving the interrupt, FPGA uses USB interrupt transmission to report to the host that there is an external call, and the PC application software will prompt the user to choose to pick up or reject the call. After picking up the phone, FPGA will connect the call after receiving the command, and then the voice data will be transmitted bidirectionally through USB synchronous transmission. When the user dials out, the process is the same as when a call comes in.

2 System Hardware Module Design

2.1 System Hardware Block Diagram

This design uses FPGA as the core control device, and its control object is the USB2.0 interface device EZ-USB FX2 CY7C68013A-56. Figure 2 is a typical circuit connection diagram of FX2 USB and FPGA when the EZ-USB device works in Slave FIFO mode .

2.2 Introduction to FPGA and USB

The core control device FPGA in the design uses Ahrea's EP2C8Q208C8, while the USB device device uses Cypress's CY7C68013A-56. EP2C8Q208C8 is one of the Ahera Cyclone II series devices. Cyclone II FPGA is a low-cost FPGA produced based on Stratix II's 90 nm process. The application of Cyclone II FPGA is mainly positioned in the terminal market, such as consumer electronics , computers, industry and automobiles. EP2C8Q208C8 has 2 phase-locked loops (PLLs) and 8 global clock networks, 8 256 logic units (LEs), 36 M4K RAMs, 18 multiplier modules, and 138 available I/Os. EP2C8Q208C8 has the advantages of low cost, high performance, low power consumption and scalability to IP-PBX systems (enough I/O interfaces), so this device is selected as the control device of the system.

The CY7C68013A-56 device is the first integrated microcontroller that includes USB2.0. It integrates an enhanced 8051, an intelligent USB serial interface engine (SIE), a USB data transceiver, three 8-bit I/Os, 16-bit address lines, 8.5 KB RAM, and 4 KB FIFO. The enhanced 8051 core is fully compatible with the standard 8051, and its performance can reach more than three times that of the standard 8051. Figure 3 is the structural block diagram of the CY7C68013A-56.

The CY7C68013A device uses a 4 KB FIFO for data transmission, and contains 7 endpoints: EPOIN/OUT, EPIIN, EPIOUT, EP2, EP4, EP6, and EP8. Among them, EPO, EPIIN, and EPIOUT are three 64 B buffer endpoints that can only be accessed by firmware. EP0 is the default data input and output port cache, which works in control transmission by default. EPIIN and EPIOUT are independent 64 B caches that can be configured as block transmission, interrupt transmission, or synchronous transmission. Endpoints 2, 4, 6, and 8 are large-capacity and high-bandwidth data transmission endpoints that can be configured to various bandwidths to meet actual needs. Endpoints 2 and 6 can be configured to 512 B or 1 024 B per frame, and can be configured to 2, 3, and 4 levels. Then EP2 and EP6 can be configured to a maximum of 4 KB cache; endpoints 4 and 8 can be configured to a 512 B cache per frame.

3 System Software Design

3.1 USB Firmware Design

Since the design uses FPGA to control USB devices for voice phone communication, three USB transmission modes are used in the USB part: control transmission, interrupt transmission, and isochronous transmission. Control transmission is used to implement the standard request of the device enumeration host and the manufacturer's customized request; interrupt transmission is used to realize the device to wake up the host, and it is the only transmission method for the device to actively send data to the host; isochronous transmission is used to realize the two-way synchronous transmission of voice data. The focus of USB Firmware design is the voice communication segment.

CY7C68013A has three working modes: PORTS, Slave FIFO, and GP1F. PORTS mode is the most basic data transmission mode, and its data transmission requires direct participation of the CPU, which is suitable for occasions where the transmission rate requirement is not high; GPIF mode is the host mode, and the internal host controls the endpoint FIFO; Slave FIFO mode is the slave mode, and the external controller, such as FPGA, DSP. The application uses the asynchronous FIFO mode, uses the internal 48 MHz clock, and the automatic mode, and the firmware program is written based on the firmware program framework provided by Cypress, and its own configuration code is added to its initialization function.

In the whole system, the firmware of CY7C68013A mainly completes the following tasks: initializing USB device; communicating with the host as USB interface and transmitting data; using the Slave FlFO interface of CY7C68013A device to control the data transmission between USB device and external controller. Therefore, the main program of the same device is relatively complex. In addition to the above TD_lnit() initialization, a large number of functions are required, but the basic structure is relatively simple, including 3 processes: initialization of USB controller; main function, including code for processing standard device requests; interrupt processing, including program code for processing various interrupts. Figure 4 shows the main program flow of the same device.

3.2 USB driver Program

The USB system software consists of the software in the host and the software in the device. The software in the USB host mainly includes the USB device driver (USBDD), USB bus driver (USBD) and USB host controller driver (HCD).

The USB device driver (or client driver) is at the top level. It supports drivers for specific device classes and is responsible for communicating and reading and writing control with its corresponding USB devices to implement special functional applications of each USB device. Each type of functional unit connected to a USB device must have a client driver. The client driver regards the USB device as a collection of accessible endpoints. USB devices can be controlled and communicate with their functional units. The USB device driver sends requests to the USB bus driver via I/O request packets (IRPs). These request packets initiate a given transfer. This transfer can come from a USB target device or be sent to a USB device.

The USB bus driver (USBD) is a module between the host controller driver and the USB device driver. It corresponds to the USBD of the USB protocol and is provided by the USBD.SYS module in the Windows system. It is software that provides support for the USB bus and protocol on a certain operating system. It is independent of USB devices and USB device drivers, and controls them and provides a unified programming interface.

The USB host controller driver (HCD) is at the bottom layer, which is responsible for abstracting the host controller and providing low-level support for USB.

3.3 PC software design

The software design of the PC side adopts object-oriented programming, which is divided into core classes (including Provider, Data, Net) and application classes (including UI, Call, Record). The core class provides support for hardware, operating system and network environment, and the application class provides support for user operations based on the core class. The Provider class defines the read and write operations of the USB device, and provides methods for reading data (readusb()) and writing data (writeusb()); the Data class includes the definition of address data (Address), audio data (Audio) and control data (Command), and provides data decomposition methods (Decompose()) and combination methods (Compose()); the Net class provides support for the network, including the selection of network protocols and the reception and transmission of data. The UI class provides support for the user interface, including windows, dialog boxes, etc., to realize the basic user framework and application entry; the Call class provides call functions; the Record class provides phone recording functions; other application classes can be extended according to different application requirements. The specific structure is shown in Figure 5.

4 Conclusion

The flexible interface and programmable features of USB can simplify the design of external hardware and improve system reliability. The USB2.0 controller CY7C68013A is also widely used in many data transmission fields. FPGA has become a basic device in the fields of communications, computers, consumer electronics, etc. The USB device introduced here is an embedded system based on FPGA. The system hardware and software have modular characteristics and can be easily transformed into a voice control system for other applications (except DAA). The application of this design can save a lot of manpower and material resources. It has great promotion significance and use value.