Research and design of data acquisition control module based on FPGA

0 Introduction

Data acquisition and control system is a closed-loop control for real-time acquisition, testing and feedback control of various physical quantities in production processes or scientific experiments. It plays an important role in many fields such as industrial control, military electronic equipment, medical monitoring, etc. Among them, the data acquisition part is particularly important, and the traditional data acquisition system usually uses a single-chip microcomputer or DSP as a controller to control the operation of ADC, memory and other peripheral circuits, which reduces the acquisition speed and efficiency. In recent years, the development of microelectronics technology, such as large-scale integrated circuits and ultra-large-scale integrated circuits, has provided a good material basis for the development of data acquisition systems. As a result, the device develops towards modularization and monolithicization, the software used develops towards real-time high-level language and software modularization, and the interface develops towards standardization. Due to the high clock frequency of FPGA and small internal delay, all control logic is completed by hardware, which is fast and efficient. At the same time, it has very powerful hardware description language and simulation tools to facilitate the verification of the correctness of the results. Based on the above considerations, FPGA is used as the control processor in the design. The design of the VGA interface highlights the compatibility of the module and makes it easier to intuitively display the collected data.

1 Overall system design

The complete data acquisition process usually consists of data channel selection, sampling, storage, and display, and sometimes the data must be properly processed. Among them, the control module plays a core role. As the center of control signal generation and processing, it monitors and manages these peripheral circuits in real time. In the design process, FPGA is used as a controller to complete the control of the A/D converter and store the collected data in a certain storage unit. Through the VGA interface protocol, it is finally displayed on the monitor. In the specific peripheral circuits involved, the data acquisition part mainly uses ADC0809 as a data acquisition chip to perform A/D conversion on the input analog quantity; the data cache part uses 6116 as a storage chip to cache the data collected by 0809; the key control part uses 8 keys to control the conversion channel selection of 0809; the graphic display part outputs a standard VGA signal and uses a CRT display to display real-time waveforms. Since the controllers that control external devices in the design are all completed by FPGA, the workload of FP-GA is very large, so the FPGA chip used is the 300,000-gate EPF10K30 in the FLEX series.

2 Implementation of the master control module based on FPGA

The working principle of the main controller is shown in Figure 1.

The control signal for ADC0809 is generated through an A/D conversion controller. After ADC0809 is started, A/D conversion will be performed at a certain frequency. At the same time, the data will be latched into the A/D conversion control module through a data latch signal. This latch signal will be used as the write input control signal of the RAM controller. When the write control signal of the RAM read-write controller is valid, the write enable valid signal of the RAM will be turned on, and the collected data will be written to the 600th address unit of the RAM. Then the RAM controller will move the data in the RAM up by one bit. After the shift is completed, a data update completion signal will be generated, and then an internal control signal will be passed to allow data to be read from the RAM. If the read data in the RAM is enabled, whenever the VGA display controller issues a read data command, the RAM read-write controller will turn on the read valid signal of the RAM, read the data in the RAM, and display it through the timing control and output signal of the VGA controller. There are 8 external key parts, and these 8 keys control the selection of the 8 channels of ADC0809. The function of the keyboard controller is to scan the row and column values ​​of the pressed key and synthesize the key value. It is converted into key values ​​0 to 7, and finally controls the selection of 8 analog input channels.

2.1 Design of VGA display controller

Common color displays are generally composed of cathode ray tubes (CRTs). Colors are composed of three primary colors: red, yellow, and blue (R, G, B), and image display is solved by line-by-line scanning. Its lead wires contain a total of 5 signals: R, G, B three primary color signals; HS; horizontal synchronization signal; VS; field synchronization signal.

The timing drive of these five signals of the VGA display must strictly follow the "VGA industrial standard", that is, the 640×480×60 mode, otherwise the VGA display will be damaged. Here, the controller has 2 input signals and 6 output signals. CLK is connected to an external crystal oscillator, and its crystal oscillator frequency is 50 MHz. Since the crystal oscillator frequency required by the VGA industrial standard is 25 MHz. Therefore, in this controller, the clock must first be divided by two. RD is an 8-bit data volume, which receives the data read from the RAM. The output signal READ is used to control the RAM control module to turn on the RAM read valid signal. As long as READ changes, it will enter the data read state, and the data read out will be received by RD. HS and VS are the horizontal synchronization signal and the field synchronization signal respectively, and R, G, and B are the three output signal lines. The display waveform is achieved by changing the values ​​of the three output signals R, G, and B.

Each data read out actually corresponds to a pixel. Since the voltage value range collected here is 0~5V, the corresponding data amount converted by ADC0809 is 0x00~0xFF, so when designing, just make the specific value received by RD correspond to a row in the display. The specific implementation can realize row positioning by using comparison statements, and at the same time, the column auxiliary register LLV can be added by 1, so that a continuous waveform can be realized. These points are connected to form a complete waveform, and the generation of the line synchronization and field synchronization signals is respectively generated by the internal signals CC and LL according to the known input clock, through the counter counting method, to reach the frequency required by the industrial standard. [page]

2.2 Design of A/D conversion controller

In this design, the state machine is used to control the A/D conversion. The state diagram of controlling the ADC0809 sampling is shown in Figure 2.

In state ST0, 0809 is initialized and then enters state ST1; in state ST1, ALE and START signals are valid, and the EOC signal becomes low level, entering the conversion state ST2. At this time, it is necessary to test the 0809 working status signal EOC. If it is low level, it means that the conversion has not ended, and it is still necessary to stay in the ST2 state and wait until it becomes high level to indicate that the conversion is over. When the next clock pulse arrives, it turns to state ST3. In state ST3, the state machine sends a converted 8-bit data output enable command to 0809. This state cycle can also be used as a data output stabilization cycle so that reliable data can be locked into the latch in the next state. In state ST4, the state machine sends a latch signal to the latch in the FPGA to latch the data output by 0809.

2.3 Design of RAM read-write controller

In the module design, the RAM read-write control module is divided into a read control module, a write control module and a read-write state conversion module. The two input signals in the write control module are connected to the data latch and conversion output of the A/D conversion control module respectively. When the latch signal is enabled, a write signal is issued to store the data in the 600th address space of the external RAM, and then the previous data is moved forward to achieve timely data update. The control signals of the read control module are connected to the write update completion signal and the read signal respectively. When the write update completion signal is enabled, as long as the read signal is received, the data of the first 600 address spaces (one field) of the external RAM are read in sequence.

2.4 Design of keyboard scanning controller

The keyboard control module consists of four modules, including: clock frequency division module, row key value output module, key value latch module and key value synthesis module. The key value latch module latches the row and column information of the pressed key and passes it to the key value synthesis module, which looks up the table with the result output by the row key output module and finally determines the key value.

3 Simulation Results

The graphical input method of the Max+PlusⅡ simulation platform is intuitive, in line with the habits of traditional digital system designers, easy to design interfaces, easy to implement simulations, and easy to observe signals. Based on the above considerations, this platform is used to implement various functional modules using the hardware description language VHDL. The timing simulation results of the A/D conversion controller and VGA display controller modules are shown in Figures 3 and 4.

4 Conclusion

The data acquisition control module here is mainly based on FPGA. Based on the idea of ​​software hardware, we focus on the realization of the main control module. Since FPGA is used as the control processor, it is fast and efficient, and the standard VGA interface makes the system more convenient to use. The keyboard-controlled multi-channel switching also lays the foundation for the realization of multi-channel acquisition.