The original meaning of MOSFET is: MOS (Metal Oxide Semiconductor), FET (Field Effect Transistor), that is, a field effect transistor that uses the gate of the metal layer (M) to control the semiconductor (S) through the effect of the electric field through the oxide layer (O).
Power field effect transistors are also divided into junction type and insulated gate type, but usually mainly refer to the MOS type (Metal Oxide Semiconductor FET) in the insulated gate type, referred to as power MOSFET (Power MOSFET). Junction power field effect transistors are generally called static induction transistors (Static Induction Transistor - SIT). Its characteristics are that the gate voltage is used to control the drain current, the drive circuit is simple, the required drive power is small, the switching speed is fast, the operating frequency is high, and the thermal stability is better than GTR, but its current capacity is small and the withstand voltage is low. It is generally only suitable for power electronic devices with a power not exceeding 10kW.
For MOSFET, Miller Effect refers to the effect that the distributed capacitance (gate-drain capacitance) between its input and output amplifies the equivalent input capacitance value under the inverting amplification effect. Due to the Miller Effect, a platform voltage will be formed during the MOSFET gate drive process, causing the switching time to become longer and the switching loss to increase, which has a very adverse effect on the normal operation of the MOS tube.
This article analyzes the MOS tube turn-on and turn-off process and the formation of the Miller platform in detail. Then, combined with the actual application circuit, it explains the causes and possible consequences of the voltage spike in the MOSFET switch, and gives the corresponding solutions.
MOSFET structure and distribution of parasitic capacitance
Figure 1 shows the structure of a vertical MOSFET, which is a double diffusion structure consisting of a P region and an N+ source region. The drain and source are placed on both sides of the wafer. This structure is suitable for manufacturing high-power devices. This is because the current level between the drain and source can be increased by increasing the length of the epitaxial layer, thereby improving the device's breakdown voltage capability. In addition, the parasitic body diode of the MOSFET can also be clearly seen from the figure.
Figure 2. Parasitic capacitance and equivalent circuit of MOSFET
The parasitic capacitance of MOSFET mainly includes gate-source capacitance (Cgs), gate-drain capacitance (Cgd) and drain-source capacitance (Cds). As can be seen from the left figure in Figure 2, Cds is formed by the junction capacitance between the drain and the source, and Cgd is the coupling capacitance between the gate and the drain. Cgs is more complex, consisting of the capacitance Co between the gate and the source metal electrodes, the capacitance CN+ between the gate and the N+ source diffusion region, and the capacitance Cp between the gate and the diffusion region P region.
Considering the wide application of inductive loads, this paper uses inductive loads to analyze the formation of the Miller platform. Since the switching time of the MOS tube is extremely short, the inductive current can be considered constant and treated as a constant current source. Figure 3 shows the gate drive circuit and the current and voltage waveforms of the MOS tube when it is turned on.
Starting from time t0, the gate drive current charges the gate-source capacitance Cgs. When Vgs rises from 0V to Vgs(th), the MOS tube is in the cut-off state, Vds remains unchanged, and Id is zero.
From time t1, the MOS transistor begins to conduct because Vgs exceeds its threshold voltage. Id begins to rise, and part of the current of the inductor current flowing through the freewheeling diode DF is commutated and flows into the MOS transistor. However, the diode is still conducting at this time, and the voltage across the MOS is still clamped by the diode and remains unchanged. The driving current only charges the gate-source capacitor Cgs. At time t2, Id rises to the same level as the inductor current, and the commutation ends.
During the period of t1-t2, Vds will drop slightly during the process of the inductor current rising. This is because the di/dt of the increase in Id will form a voltage drop on the stray inductance such as the lead inductance, so the voltage across the MOS tube will drop slightly.
During this period of time, the MOS tube is in the saturation region.
Starting from time t2, since the current in the MOSFET has risen to the current in the inductive load, the voltage across the MOS tube is no longer clamped by VDD. Therefore, the inversion layer channel between the drain and source is no longer constrained by VDD and is wedge-shaped, Vds begins to decrease, and the gate drive current begins to charge Cgd. The drive current is all used to charge Cgd, and the gate voltage Vgs remains unchanged and presents a plateau period, which is called the Miller platform.
The Miller platform is maintained until the Vds voltage drops to the point where the MOS tube enters the linear region. It can be noted that during the Miller platform period, the slope of the Vds voltage drop is divided into two sections, which is related to the structure of the MOSFET. This is because the Cgd capacitance changes at different stages of conduction.
At this stage, the MOS tube is still in the saturation region.
By the way, here is why the drain-source voltage starts to drop after the MOSFET enters the Miller platform.
Before entering the Miller platform, the drain-source voltage is clamped by the diode to keep VDD unchanged, and the conductive channel of the MOS tube is in a pinch-off state. When the MOSFET current is the same as the inductor current, the drain of the MOSFET is no longer clamped. This means that the pinch-off state of the conductive channel caused by the VDD clamp is released, and the channel close to the drain side of the conductive channel gradually widens, thereby reducing the on-resistance of the channel. When the drain current Id remains unchanged, the drain-source voltage Vds begins to decrease.
When the drain-source voltage Vds drops, the gate drive current starts to charge the Miller capacitor Cgd. Almost all the drive current is used to charge Cgd, so the gate voltage remains unchanged. This state is maintained until the channel is just in the pre-pinch-off state and the MOS tube enters the linear resistance region.
From t3, MOSFET works in the linear resistance region. The gate drive current charges Cgs and Cgd at the same time, and the gate voltage starts to rise again. As the gate voltage increases, the conductive channel of MOSFET also begins to widen, and the conduction voltage drop will further decrease. When Vgs increases to a certain voltage, the MOS tube enters the fully on state.
Now let's summarize how the MOSFET is turned on during the driving process. Figure 9 shows the position of the MOSFET output curve corresponding to different stages during the turn-on. When Vgs exceeds its threshold voltage (t1), the Id current increases with the increase of Vgs. When Id rises to the value of the inductor current, it enters the Miller plateau period (t2-t3). At this time, Vds is no longer clamped by VDD, and the MOSFET pinch-off area becomes smaller until the MOSFET enters the linear resistance area. After entering the linear resistance area (t3), Vgs continues to rise, the conductive channel also becomes wider, and the MOSFET conduction voltage drop is further reduced. The MOSFET is fully turned on (t4).
Influence of Miller Effect on MOSFET Switching Process
The following uses the motor control circuit in Figure 10 to illustrate the impact of the Miller effect on the MOSFET turn-on and turn-off process. In the control circuit in Figure 10, when the upper tube is turned on, VDD excites the motor through Q1 and Q4; when the upper tube is turned off, the motor is demagnetized through Q4 and Q3. During the entire working process, Q4 remains on, and Q1 and Q2 are turned on alternately to excite and demagnetize the motor rotor.
Figure 11 and Figure 12 are the driving voltage test waveforms when the upper and lower tubes are turned on and off. It can be clearly seen that when the upper tube is turned on and off, a spike will be generated on the gate of the lower tube. The spike voltage increases the risk of the upper and lower tubes being turned on at the same time. In severe cases, a very large current will flow through the upper and lower tubes at the same time, damaging the device.
Figure 12. Test waveforms when the upper tube is turned off and the upper tube is turned on
The waveform that appears when the lower tube is turned on and off is a parasitic turn-on phenomenon caused by the drain-gate capacitance (as shown in Figure 13). After the lower tube is turned off, the upper tube Miller platform ends, and the bridge arm midpoint voltage rises from 0 to VDD, and a steep dV/dt is generated between the source and drain of the MOSFET. The current generated in the drain-gate capacitance will flow to the gate, through the gate resistor to the ground, which will generate a voltage drop on the gate resistor. In this case, the upper and lower tubes may be turned on at the same time, damaging the device.
Rgoff is the driver off resistance, Rg,ls(int) is the intrinsic resistance of the MOSFET gate, and Rdrv is the resistance of the driver IC. From formula (1), it can be seen that this voltage is positively correlated with Rgtot and Cgd.
1. Reduce Rgtot. From formula (2), we know that Rg,ls(int) is determined by the device itself, and Rdrv is determined by the driver IC, so generally we choose a suitable Rg to balance the Vgs bouncing voltage.
2. Selecting a MOSFET with low Crss/Ciss (i.e. Cgd/Cgs) helps reduce the Vgs peak voltage. Alternatively, a capacitor can be connected between the gate and source of the MOSFET to absorb the leakage current generated by dV/dt. Figure 15 shows the switching waveform after a 5.5nF capacitor is connected in parallel to both ends of the GS of the lower tube. It can be seen that the voltage is significantly reduced from 3.1V in Figure 11 to 1.7V, which greatly reduces the risk of the upper and lower tubes being connected.
Figure 15. Waveform of 5.5nF capacitor in parallel with the lower GS
Similarly, when the upper tube is turned off to the end of the Miller platform and before the lower tube is turned on, the midpoint voltage of the bridge arm drops from VDD to 0, and a steep dV/dt is generated between the source and drain of the MOSFET, which will generate a negative voltage on the gate.
At the same time, it can be observed from Figures 11 and 12 that the Miller platform phenomenon does not occur during the opening and closing of the lower tube. This is because when it is opened and closed, the current in the Motor flows through the body diode of the lower tube, and the voltage across DS is very small, so the Miller platform cannot be formed.
In fact, it is not easy to use a discrete device well. If you just look at its function, it seems very simple. It is nothing more than being used to switch circuits.
Details
Published on 2022-10-29 22:11
I have known about the existence of the Miller platform for a long time, but I never paid much attention to it. I have never paid attention to it in my daily use. Today I understand it.
In fact, it is not easy to use a discrete device well. If you just look at its function, it seems very simple. It is nothing more than being used to switch circuits.
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
