Design of motion controller based on DSP and FPGA

Motion control technology is the key technology of CNC machine tools, and its technical level will directly affect the development level of a country's equipment manufacturing industry. At present, multi-axis servo controllers are increasingly used in motion control systems. They have high integration and flexibility, can complete complex logic processing and control algorithms in the motion control process in real time, and can realize multi-axis high-speed and high-precision servo control. This paper selects DSP and FPGA as the core components of the motion controller and designs a general motion controller. Among them, DSP is used for motion trajectory planning, speed control and position control functions; FPGA completes the fine interpolation function of the motion controller, which is used to accurately calculate the control pulses of stepper motors or servo drive elements, and receives and processes pulse position feedback signals. This paper describes the overall structure, hardware design and software design of the motion controller.

1 Overall system design

The overall performance indicators of the motion controller are: used as a separate motion controller, the control signal is output in digital form, and it can control the servo motor of four axes; the maximum pulse output frequency is 4MP/s, and the maximum frequency of the encoder feedback signal that can be processed is 4MP/s; it can receive and process 4 encoder feedback signals; it can process digital input signals such as origin signal, positive and negative direction signal, in-position signal and emergency stop signal; it provides 16 digital output signals and 16 digital input signal interfaces. The motion controller uses DSP and FPGA chips as the main control chips, mainly including DSP module, FPGA module, FPGA peripheral circuit module and digital input and output interface module.

The motion controller based on DSP and FPGA can complete complex trajectory calculations in real time, and can fully demonstrate the advantages of the motion controller by utilizing the high-speed digital signal processing function of DSP and the advantages of low power consumption and high main frequency of FPGA. The motion controller combining DSP and FPGA can easily modify the control strategy of the system, correct the control parameters, and make the equipment have good reliability and maintainability, and also reduce costs. The system can also adopt more intelligent control strategies, with flexible structure, strong versatility, suitable for modular design, can improve algorithm efficiency, and is easy to maintain and expand. The principle block diagram of the overall design scheme is shown in Figure 1.

2 System Hardware Design

2.1 DSP module

This controller uses TI's TMS320F2812 as the main control chip, which is a 32-bit control-specific DSP with built-in FLASH and a main frequency of up to 150 MHz. It has digital signal processing, event management and embedded control functions and is suitable for occasions where large quantities of data are processed.

The TPS767D318 chip produced by TI is selected to implement the power supply design of TMS320F2812, converting the 5 V power supply into 3.3 V and 1.8 V respectively. SRAM is a commonly used peripheral memory for DSP. It has the advantages of simple interface and fast reading and writing speed, so the 64 KB random access memory CY7C1021 is selected as the memory expansion chip. The interface circuit between DSP F2812 and CY7C1021 is shown in Figure 2.

The reset circuit design uses TI's TPS382x series voltage monitoring circuit, which can form a monitoring circuit without peripheral circuits. The SCI module is used to expand the RS-232 and RS-485 serial communication interfaces; the CAN module is connected to the external CAN industrial field bus; the external interface is used to connect to the FPGA and expand the digital input and output.

2.2 FPGA Module

The FPGA chip selected is Altera's Cyclone series EP1C6TC44C8, which is a high-performance, low-power FPGA. EP1C6TC44C8 has two phase-locked loops, including 5,980 logic units, equivalent to a scale of 120,000 gates, and also includes an internal RAM with a maximum frequency of 200 MHz and 92,160 bits. The number of logic gates, frequency, and pin I/O resources of this chip can well meet the design requirements of the motion controller. Since the control object of this system is the servo motor, the design mainly uses the I/O port of EP1C6TC44C8 to design the input and output of the motor control signal, the input of the encoder signal, and some digital input and output. In addition, after the entire hardware system design is completed, the chip can also reconfigure the hardware through the JTAG interface, which can increase the flexibility of system design.

2.3 FPGA peripheral circuit module

The X-axis servo motor control circuit is shown in Figure 3. The Y-axis, Z-axis, and U-axis servo motor control circuits are the same as those of the X-axis.

(1) Input and output switch interface design. The input signals mainly include limit switch signals LIMX+, LIMX-~LIMU+, LIMU-, servo alarm signals ALMX~ALMU and return to zero signals HMX~HMU. The output signals mainly include servo enable signals SRVX~SRVU and reset signals RSTX~RSTU. After detecting these signals, the specific triggering signals are determined. If the limit signal is triggered, the movement of the corresponding motor in that direction is immediately stopped until the limit is eliminated, and the motor can continue to move in that direction; if the return to zero signal is triggered, the motor waits for the input of the Index signal and immediately lets the motor run in the reverse direction to the return to zero distance set by the user as the mechanical zero point; when the servo alarm signal is input, the program immediately stops the movement of the motor until the user clears the alarm.

(2) Output control pulse circuit design. The output control pulse signal is the 4-channel pulse control output signal of the servo motor. This control adopts the "pulse + direction" instruction. Since each control axis has a pulse and direction signal, there are 8 output signals in total. The output control pulse signal is output by the FPGA. It must first undergo level conversion to convert the 3.3 V of the FPGA's I/O pin to 5 V, then undergo optoelectronic isolation, and then pass through the Schmitt trigger for shaping before output. Since the pulse and direction signals need to be differential, the signal is connected to the differential line driver before output. XPLS~UPLS are pulse signals, and XDIR~UDIR are direction signals. The differential line driver is composed of AM26LS31. The function of this circuit is to convert the input unipolar square wave signal into a pair of motor drive signals with opposite polarities. Its high impedance output state is guaranteed when the power is off.

(3) Feedback pulse processing circuit design. The encoder signal of the servo motor is directly connected to the motor driver, and the driver provides three pairs of differential signals A+, A-, B+, B-, Z+, and Z- as feedback. These three pairs of signals are interfered by the large power supply inside the driver. When the motor rotates, many glitches will appear in the signals emitted. Directly connecting them to the FPGA will cause misjudgment, so the three pairs of signals are converted into single signals A, B, and Z through the differential circuit. The differential circuit is composed of AM26LS32. The function of this chip is opposite to that of AM26LS31. The function of this circuit is to convert a pair of encoder feedback signals with opposite polarities into a unipolar square wave signal. The A and B channels are orthogonal encoding pulses, and the Z channel generates a low-level pulse per rotation, which is used for precise positioning when returning to zero.

2.4 Digital Input and Output Interface Module

Considering the scalability of the system and the number of GPIO ports of the DSP, this motion controller is designed with 8 channels on the DSP and FPGA, for a total of 16 digital input and output channels. All digital input and output signals of the motion controller are processed by photoelectric isolation, and each signal is subjected to corresponding digital filtering to eliminate noise signals. The digital input channel can be customized according to the user's requirements, and is used for the input of zero point and limit signals, etc.; the digital output channel is used for the output of each axis direction and pulse signal, as well as the start and stop control of some external devices, etc.

3 System Software Design

The software design adopts a modular design method. The overall structure of the program is based on data management and position speed control, with I/O port control, logic control, interpolation operation, etc. as interrupt tasks or sub-function tasks. Position speed control is mainly responsible for monitoring and adjusting the real-time motion state; I/O port control is mainly responsible for auxiliary tasks such as scanning input ports and setting output ports.

The DSP control program is mainly composed of a timer interrupt. After the main program is started, it first completes the initialization of TMS320F2812 and some basic configurations of the system, and then enters a waiting state. The motion control function is implemented in the servo interrupt service program. The basic flow of the main program and the servo interrupt service program is shown in Figure 4.

FPGA mainly completes the fine interpolation function of the motion controller and uses the digital integration method for interpolation [1]. The digital integration method is divided into three states: (1) State WAIT, waiting for the interpolation signal; (2) State L1, judging the total number of pulses; (3) State L2, the integral accumulator accumulates once. If there is an overflow, the corresponding output pulse is high level, and the remaining accumulation times are reduced by 1.

The finite state machine of the digital integration method is shown in Figure 5.

Trigger condition T1: no start signal, the next state is WAIT, no operation; trigger condition T2: there is a start signal, the next state is L1, the operation is to initialize each register and set the busy signal; trigger condition T3: the remaining cumulative number is greater than 0, the next state is L2, the operation is that the output pulse of each axis is low level; trigger condition T4: the remaining cumulative number is 0, the next state is WAIT, the operation is that the output pulse of each axis is low level and the busy flag is cleared; no trigger condition: the next state is L1.

The specific implementation method is: the interpolation pulse generated by the timing circuit is used as the accumulation pulse of this module, and each time it is accumulated, the remaining accumulation times decrease by 1. When the remaining accumulation times is 0, the interpolation process ends.

This paper designs a universal four-axis servo motion controller. The structure design of the motion controller is modular and easy to expand, which can meet the various needs of users. In the software part, the interpolation method of the finite state machine is adopted, and the interpolation speed processing link is optimized to make the pulse output more stable. This design adopts the modular idea, each motor can be controlled separately, has a more comprehensive motion control function, higher control accuracy and faster response speed, and has reliable performance, simple hardware structure and low price.