Hardware Design of Video, Image and Voice Transmission System Based on DSP

With the rapid development of science and technology, the digital processing of video images and voice is increasingly widely used in military, scientific research, industrial and agricultural production, medical and health care and other fields. Early grain monitoring was mainly based on the collection and observation of the temperature and humidity of the granary. With the further improvement of the grain system, people have put forward higher requirements, hoping to conduct real-time image and voice monitoring inside the granary, and further strengthen the observation and prevention of pests and fires. The video image and voice transmission system based on TMS320C6201 used in this paper is applied to the monitoring of grain conditions, and is designed on the premise of meeting the above requirements.

There are two basic methods to realize the image and speech compression transmission system: one is based on microcomputer, the image and speech processing system is integrated into the microcomputer system in the form of a plug-in card through the PCI bus, and the data is exchanged and transmitted through the PCI bus or the interface on the card; the other is to run independently without the microcomputer, and use the microprocessor chip to perform digital compression and transmission of image and speech. The design introduced in this article adopts the latter method.

1 System composition and basic principles

A complete video, image and voice transmission system must not only have the function of collecting image and voice signals, but also needs to complete the analysis and processing algorithms (such as image compression, etc.) of the collected image and voice signals, and finally use a certain medium to transmit the processed signals to the terminal host for display. The analysis and processing algorithms of video, image and voice signals require a large amount of calculation, and at the same time, they must meet the requirements of real-time display, so a high-speed DSP chip is used as the data core processing unit. The basic structural model of the system is shown in Figure 1.

2 Hardware Structure

2.1 Analog video input interface design

(1) Video sampling requirements. The function of the analog video input interface circuit is to pre-process the input analog video signal and digitize it. Video sampling has two important indicators: sampling resolution and sampling frequency. Sampling resolution represents the level of image grayscale quantization. The more bits, the richer the image layers and the larger the image data volume. The sampling frequency determines the spatial resolution of the digitized image. In order to avoid distortion, it must be greater than twice the highest frequency in the spectrum of the analog video signal. In addition, the system noise introduced by the analog video input interface is required to be minimal. The principle block diagram of the DSP analog video input interface is shown in Figure 2.

(2) Analog video decoding module. The function of the video decoding module is to perform A/D conversion on analog video signals such as composite video and YC components, and extract the synchronization and clock signals therein. All conversion circuits are concentrated in one chip. According to the above requirements, the programmable digital video A/D converter SAA7111A produced by Philips was selected. It has 4 analog inputs and 2 analog signal processing channels, and the signal format can be selected by programming. The output signal can be in YUV411 (12 bits), YUV422 (16 bits), YUV422 (CCIR-656) (8 bits), RGB (5, 6 and 5) (16 bits) or RGB (8, 8 and 8) (24 bits) format. The system programs SAA7111A through the I2C bus to complete the initial configuration. The analog signal from the camera is firstly subjected to signal clamping, analog amplification, anti-aliasing filtering, and A/D conversion under the control of analog signal. Then the obtained 8-bit brightness signal and 8-bit color signal are sent to the brightness processing circuit and the color processing circuit for processing respectively to generate 16-bit YUV signal. Y(7:0) is the 8-bit digital brightness signal, and UV(7:0) is the multiplexed signal of different colors (BY and RY). The signal output format is controlled by I2C bus (the output format of YUV signal is determined by I2C bus control circuit), and the frame timing is controlled by HREF signal. In the system, the single-chip microcomputer T89C51IC2 with I2C interface and compatible with 51 series is used to control SAA7111A, that is, the sampling rate, clamping level, phase-locked loop, etc. of the analog video front end SAA7111A are programmed and set so that the entire video input interface circuit works in the pre-designed way.

(3) Use FIFO as the real-time image data input buffer. In terms of performance, ordinary frame storage cannot read the collected data while collecting. Although the use of dual-port RAM can also solve the problem of concurrent access, the address decoding required by it and the large main memory mapping space occupied (or complicated page switching) are practical problems that cannot be ignored. From the processing method of the collected data, it can be seen that for simple collection applications (no need to do pre-processing work such as superposition on the data), its system cache unit is structurally equivalent to a first-in-first-out (FIFO) queue, that is, the data collected first in the signal time sequence is read and processed by the main processing chip first. Therefore, the use of a dedicated FIFO chip can remove the complex buffer frame address decoding circuit, greatly simplifying the system design. FIFO (IDT72V3640) is used to transmit the 16-bit real-time image data VPO (0:15) converted by SAA7111A to TMS320C6201. FIFO does not have the problem of address lines, so there is no need to connect the address lines.

2.2 Selection of audio codec

Crystal's CS4231A chip is used as the core audio codec (CODEC) module. The CS4231A multimedia chip provides a flexible and universal audio front end for the system. It is a 16-bit stereo device that includes complete on-chip filtering, analog mixing, and programmable gain and attenuation adjustments. The CS4231A supports common sampling frequencies such as 8, 9.6, 11.025, 16, 22.05, 32, 44.1, and 48kHz. Such a wide range of sampling frequencies can meet various application requirements from telecommunications to audio. The CS4231A uses two crystal oscillators with frequencies of 16.9344MHz and 24.576MHz as the clock source for the sampling frequency.

CS4231A provides both parallel and serial interfaces, supports DMA and interrupt working modes, and can therefore be connected to DSP in a variety of ways. The most effective way is used here: the serial interface transmits audio data, and the parallel interface transmits control information. CS4231A uses a serial audio data interface that is compatible with the DSP's McBSP (multi-channel buffered serial port). This interface provides a dedicated channel for serial audio data without occupying the bandwidth of the DSP's EMIF. In the serial data stream, CS4231A transmits the left channel data first and then the right channel data, and the high bit is in the front during transmission (compatible with the working mode of McBSP). The CS4231A serial port is connected to the DSP's McBSP through the four 2-to-1 multiplexers of the multiplexing chip CBT3257. This setting allows the McBSP to be connected to the CS4231A on the board, or to its own specific application daughter board at any time. CS4231A contains an 8-bit parallel control/status interface, which is controlled and read by mapping the interface register to the DSP's EMIF space. This separates the control interface from the audio data, avoids signal multiplexing on a single bit stream, and simplifies software driver design. CS4231A is a 5V device, and DSP is a 3.3V device. When they are connected to each other, they get parallel control signals, and the signal conversion must be performed through the bus transceiver.

The CODEC module supports multiple inputs of linear and microphones: the audio amplifier is used to prevent and filter the microphone input signal; the linear input is sent to the CS4231A after passive filtering and AC coupling, and the input socket can be used to connect a stereo source. The selection of the left and right input channels and their respective gains can be independently controlled by software. The CODEC also includes a linear output that can be attenuated by DSP software.

2.3 System Expansion Memory Interface Design

(1) Program storage and data presetting. Since the video motion estimation and image processing algorithms are required to automatically adapt to different imaging conditions, multiple algorithms must be stored as options. Therefore, it is required to use a large-capacity memory or multiple small-capacity memories. The off-chip 8-bit or 16-bit program memory must be configured in the CE1 space of the TMS320C6201EMIF (external memory interface). This is because: ① After the system is reset, the boot program can only be loaded from CE1. ② Among the four storage spaces of EMIF, only CE1 can interface with the 8-bit or 16-bit "narrow storage space". According to the size of the pre-stored program and data, use a Flash ROM of corresponding capacity.

(2) Use SDRAM to expand the system's external data dynamic storage unit. In a high-speed DSP video processing system, the function of the data storage is to temporarily store image data. However, the on-chip data RAM of the high-speed DSP device TMS320C6201 is only 3Mb, which cannot guarantee the processing of large amounts of data. Therefore, the off-chip data storage must be expanded. The reasons are: ① The system's requirements for the capacity of the external data storage. If the image resolution is required to be 320×240 and the grayscale layer of each sampling point is 8 bits, then the storage space occupied by a single-color image is 256KB, and the storage space occupied by a three-color image is 3×256KB. If the processing algorithm involves n frames of images, the storage space is n times. Generally speaking, the DSP video processing system allows selection between multiple algorithms when working, and the data storage capacity it requires should be estimated based on the algorithm involving the largest number of frames. ② The storage arrangement of image data during video image processing. According to the characteristics of this system, in the composition of the internal data RAM and the off-chip data RAM, in order to obtain a faster processing speed, attention must be paid to the storage location of the data. Here, the principle of data storage is given according to the nature of the video image processing algorithm: (a) Intra-frame processing algorithm. Only part of the data of the current frame is used for processing. The amount of data to be stored is very small. At this time, the video data to be processed and the processed video data can be stored in the on-chip RAM at the same time. (b) Inter-frame processing algorithm. When the amount of data involved exceeds 2 frames, the data to be processed and the processed data are stored in SDRAM, and the on-chip RAM only stores the intermediate results of the operation. (c) When storing on-chip data, attention should be paid to address conflicts. ③ Selection of SDRAM model. In order to reserve sufficient space for system image compression processing, the MT48LC8M16A2 (16MB) SDRAM is selected. According to the DSP data line is 32 bits wide, two MT48LC8M16A2s are selected for expansion, and the total expanded storage capacity is 32MB.

2.4 System Ethernet Interface Design

This system uses Ethernet as the transmission medium. However, there is no DSP with built-in Ethernet interface. Therefore, the Ethernet controller RTL8019AS is used to form an Ethernet interconnection interface with the DSP.

RTL8019AS is an Ethernet controller produced by Taiwan Realtek Company, which supports IEEE802.3; supports 8-bit or 16-bit data bus; has built-in 16KB SRAM for transceiver buffer; full-duplex, with 10Mbps transmission and reception at the same time; supports 10Base5, 10Base2, 10BaseT, and can automatically detect the connected medium, which accounts for a considerable proportion in ISA bus network cards. RTL8019AS has 3 interface modes with the host: jumper mode, PnP mode and RT mode.

In order to simplify the software and hardware design of the DSP network interface, the remote bootstrap loading function is not used, and the jumper interface mode is selected. The DSP's extended I/O port is used instead of the jumper to initialize the configuration of RTL8019AS. This not only saves the function of 93C46, but also avoids the trouble of changing the resource configuration with the jumper. The bus interface of RTL8019AS is compatible with the ISA bus. Although it cannot be directly interfaced with the DSP's external bus, direct interface can be achieved by performing some simple logic transformations. In addition, the bus level of DSP is 3.3V, while the interface level of RTL8019AS is 5V, so a level converter must be used when the two are interfaced.

2.5 Design of power module and reset circuit

The power supply of TMS320C6201 uses two voltages: the core voltage is 1.8V and the I/O voltage is 3.3V. DSP has power-on sequence requirements for these two voltages, requiring the core power supply (CVdd) to be powered on before the I/O power supply (DVdd). For this reason, two sets of power modules are used in the selection of power modules, and the complementary mode is formed through the dial switch, so that the system can continue to work when one set of power modules fails, which enhances the reliability of the system. The two sets of power modules are: PT6405B (5V～3.3V) and PT6502B (5V～1.8V) produced by PT for TI's DSP. This type of power module has the advantages of stability and large rated current (3A); the other set is produced by MAXIM, using DC-DC converters MAX1742 (output current 1A) and MAX1644 (output current 2A) with synchronous rectifiers, and with appropriate peripheral circuits to power the I/O and core of the DSP respectively.

In order to ensure that the TMS320C6201 chip does not produce an uncontrolled state when the power supply is lower than the required level, a power supply monitoring circuit should be added to the system to ensure that the DSP is always in a reset state during the system power-on process and when the power supply voltage is lower than a certain threshold value. The monitoring circuit uses TI's TPS3307-33d (it can also be connected to a manual reset switch).

3 Conclusion

The video, image and voice transmission system designed in this paper based on TMS320C6201 has greatly improved hardware performance compared with the system composed of dedicated chips and FPGA. The software implementation is also more flexible and convenient to modify. The system has a compact structure, high reliability and strong real-time performance, and can be widely used in military, scientific research, industrial and agricultural production, medical and health fields.