Method of using FPGA and DSP to directly control hard disk to realize storage control

1 Introduction

Data storage is an important part of the data acquisition process. At present, most data storage systems use the method of built-in industrial computers to complete data preservation tasks. This method has high system power consumption and high hardware cost, and is not suitable for systems with internal recording requirements. This system uses FPGA and DSP to directly control the hard disk for data storage, and uses a FIFO as a data cache. The design idea is relatively novel, the hardware structure is simple, and the cost is low. The method of directly controlling the hard disk can reduce the system power consumption to a minimum. It has an automatic internal recording function and can store the collected data in time. This system has been applied to a certain signal acquisition device, and practice has proved that it can meet the use requirements and can meet the storage requirements of the 80Khz data sampling rate system.

2 System Implementation Solution

This design uses FPGA and DSP to directly control the hard disk [1][2], and uses a FIFO as a data cache. The system uses DSP to complete file management and uses FPGA to implement the interface between DSP and hard disk. The specific block diagram is shown in Figure 1.

Figure 1 Solution implementation block diagram

First, the acquisition control board FPGA resets the FIFO. When data needs to be stored, the data stream directly writes the data into the FIFO. When the storage control board FPGA inquires that the FIFO status is not empty, it outputs the BIO signal to notify the DSP to start the save program. The DSP first accesses the hard disk to determine the required parameters, such as the file name to be used for the next file, the logical sector number of the saved file, etc. Then the DSP sends a save command to the hard disk. When the hard disk responds to the control command, the DSP notifies the FPGA that data can be transferred to the hard disk. When saving, the FPGA reads data from the FIFO and packs the data, changing it from 8 bits to 16 bits, and writes it to the hard disk data register. When 40M is stored, the DSP notifies the acquisition control system that a file has been filled, and the acquisition control system resets the FIFO to complete a save operation.

3 Storage Control Program Flow

After the program starts, first set SRST in the hard disk Device register to 1 to reset the hard disk. After the hard disk is reset, read MBR0 and BPB0, find the Special Sector in the FAT and check whether there is a flag bit 0x55FF. If not, it means that the hard disk is used for the first time. If so, read the parameters from it to prepare for data transmission.

(1) In order to quickly find the file name to be used, the location of the next empty cluster, the disk in use and other parameters each time the program is started, the first sector in the third cluster of the hard disk is marked as Special Sector to store these parameters.

(2) Each disk is allocated 200M of space as a reserved area. When the disk space is less than 200M, it is displayed as full. The current disk is no longer used to store data, but the next disk is used instead.

(3) The second cluster of each disk is the directory area. Since short file names are used without subdirectories, when each cluster is 16 sectors, the directory area can store a total of 256 file names.

(4) The data file size is fixed at 40M.

If the hard disk is used for the first time, the host reads MBR0, BPB0, MBR1, BPB1 in sequence until the last hard disk partition is found, and writes relevant parameters such as the size of each partition, the logical address of the partition, the logical address of the starting segment of each partition data space, the logical address of the FAT table, etc. into the Special Sector, and makes a file directory (32 bytes) and names the first file "000.dat".

When the third cluster in FAT is marked as a bad cluster, it indicates that the Special Sector has been divided on the hard disk and the hard disk parameters have been stored. The host reads the next available empty cluster from the Special Sector, calculates the position of this cluster in the FAT and reads the FAT into the RAM of C54, reads the file name and related parameters in the Special Sector and writes them into the directory area. Then query BIO, and start transmitting data when BIO is low (see storage board interface). When transmitting data, the FPGA starts the element trans_data, and the host sends XF as the start signal. The FPGA reads 2Bytes from the FIFO and writes it to the hard disk once, and writes it 256 times in succession, that is, 512 bytes of data are transmitted to the hard disk. Every time the host sends a falling edge of XF, the FPGA reads 512 bytes of data from the FIFO and stores it in the hard disk.

After the transfer of 40M data is completed, the host will fill in the FAT table according to the number of sectors transferred, and determine whether the hard disk space is less than 200M and whether the number of stored files is greater than 256. If true, the next disk partition will be used when storing data again.

4 Hard disk operation control process

We usually call the hard disk interface the IDE interface[3]. All operations on the hard disk, such as reading and writing sectors and sending commands, are completed through read-write registers. After each set of commands is sent to the hard disk, the information in the status register must be read to determine whether the hard disk has executed the sent command based on the value of the status register.

4.1 Hard disk boot operation

After the hard disk is powered on, it should be reset first. There are three ways to reset the hard disk. This design uses SRST to 1. When SRST is set to 1, the hard disk is reset immediately. At this time, you should wait at least 2ms before reading the Status register. If the value of the Status register is 80h, it means that the hard disk has been reset. The hard disk startup process is shown in Figure 2.

Figure 3 Sector read and write operation program flow chart

4.2 Sector read and write operations

First, the command parameters should be sent to the hard disk. The number of sectors to be read or written should be written into the Sector count register, the logical address of the sector should be written into the LBA High register, LBA Mid register and LBA Low register, and the device number to receive the command should be written into the Device register. The process is shown in Figure 3.

LBA = (cylinder number × number of heads + head number) × number of sectors + sector number - 1

After writing the command READ SECTOR or WRITE SECTOR to the Command register, the value of the Status register is not reliable within 400ns, so you need to wait 400ns to read the Status register. This waiting time can be spent by reading the Alternate Status register and Error register, and the read value should be discarded. When the value of the Status register is 58h, it means that the hard disk can receive or transmit data from the Data register.

4.3 DMA operation process

DMA operation is similar to I/O operation. The process is shown in Figure 4. First, the command parameters should be sent to the hard disk. The number of sectors to be read and written should be written into the Sector count register, the logical address of the sector should be written into the LBA High register, LBA Mid register and LBA Low register, and the device number to receive the command should be written into the Device register. After writing the command READ DMA or WRITE DMA into the Command register, the value of the Status register is not reliable within 400ns, so it is necessary to wait 400ns to read the Status register. This waiting time can be spent by reading the Alternate Status register and Error register, and the read value should be discarded. When the value of the Status register is 58h, the host should give the DMA initialization timing to start transmitting data.

Figure 4 DMA operation flow chart

5 Key points in design

5.1 Sampling rate issue

Data acquisition and storage systems generally have sampling rate requirements. The sampling rate is generally required to be greater than 50K to meet the requirements of fast real-time data acquisition. The slower link in this system is the hard disk storage link. The hard disk interface is designed to store data at a speed of 7.8Mbyte/S. Obviously, the acquisition rate and the storage rate do not match. The solution is to use a FIFO as a data buffer. Since the hard disk status needs to be constantly queried during operation, and the time when the hard disk status changes is uncertain, a FIFO with a larger storage depth should be used as a cache. IDT's 72V2101 meets the design requirements [5]. During operation, data is directly written into the FIFO. The FPGA queries the status of the FIFO. When it is not empty, it coordinates the DSP to access the hard disk and perform storage operations. In this way, the use of FIFO as a cache solves the rate matching problem [4]. When the sampling rate is 80k, the data flow is 5Mbyte/S. The storage speed of this system is designed to be 7.8Mbyte/S, which can meet the storage requirements of the data sampling rate system within 80K.

5.2 Hard disk storage address problem

How to store data in the hard disk is another key issue in this design, mainly considering the address of file storage and the file directory. In this design, the hard disk file is stored using the FAT32 file system, and the boot sector records the address, number, size, cluster size and other information of the file allocation table. File logical address = data segment start address + (cluster number - RootClus) × SecPerClus; data segment start address = BPB address + RsvdSecCn + FATSz32 × NumFATs. ) The file directory design uses short file names, each file name and related information occupies 32 bytes, and the second cluster of each disk is the directory area. Because short file names are used and there are no subdirectories, when each cluster is 16 sectors, the directory area can store a total of 256 file names.

6 Conclusion

This system has a large data storage capacity and lower power consumption than the traditional use of industrial computers for data storage. It is suitable for working environments with limited working environments and systems that require automatic internal recording functions. This system has been applied to a certain signal acquisition device, and practice has proved that it can meet the use requirements, the system works stably, and there is no data overflow. Of course, this system still has certain shortcomings, such as the inability to store data files of any length, and can only store files of 40M length, which needs further improvement.