Design of high-speed data acquisition system based on FPGA

Abstract: In order to improve the speed of data acquisition card and reduce the cost at the same time, a data acquisition system using pipeline storage technology is designed. The system is controlled by combining software and hardware. The ADC conversion process is completed by MAX1308 analog-to-digital converter, and the high-speed collected data is stored by using multiple Nandflash pipeline data storage mode. The hardware circuit is built, and the acquisition module, control and storage module and Nandflash storage function are implemented by writing VHDL language inside FPGA. The debugging results show that the corresponding position of the chip's read and write timing signals is accurate, there is no timing confusion, and the acquisition speed can be maintained at more than 10 MH/s. The system realizes the design requirements of low-cost, high-speed multi-channel acquisition.
Keywords: high-speed acquisition; pipeline storage; FPGA

0 Introduction
In order for the computer to process the analog quantity input by the data acquisition system, the analog quantity must be converted into digital quantity through the data acquisition system. FPGA is developed on the basis of logic devices such as CPLD. Its high integration can greatly reduce the size of the circuit board, reduce the system cost, improve the system performance and reliability, and is suitable for the application of timing, combinational and other logic circuits. A complete detection system usually has a collection and storage part. Whether it is an electrical signal, an optical signal, or a sound signal, after being received by the detector, most of them need to be converted into digital signals before being transmitted to the processor to complete the analysis and judgment process. Some of the current high-speed and large-capacity acquisition systems are often expensive. This paper mainly discusses a low-cost, high-speed, multi-channel, and reliable data acquisition system that uses FPGA and other devices for control and uses multiple Nandflash storage. This paper mainly discusses the hardware design and storage design.

1 System overall design plan
The working principle of the data acquisition system is: various information is converted into analog electrical quantity signals after passing through the sensor, and the analog quantity is converted into digital quantity signals through ADC, and then transmitted, stored, and processed. In this system, under the control of software and hardware, the system converts the collected analog signal through the A/D conversion device, and then caches the conversion result to FIFO, and then transfers it to the non-volatile Nandtlash array. Among them, FIFO can not only realize the cache function, but also solve the contradiction between the number of data bits after A/D conversion and the number of data line bits of Nandflash memory. As shown in the block diagram of the overall system design scheme in Figure 1, this system uses the microblaze processor inside the FPGA as the main controller, i.e., the software controller, while the internal logic resources of the FPGA are used to generate hardware control timing. The entire system collects and transmits data under the coordination of the two.

2 Design of Hardware Controller
The entire data acquisition system contains a data acquisition module and a data transmission module. The data acquisition module consists of an AD data conversion module and a Nandflash data storage module. The system uses a USB interface as a data transmission module, which is not the focus of this paper. In the data transmission part, this system uses DMA transmission technology. The FPGA internal circuit function module is shown in Figure 2.

Among them, ALE and WR are connected to the address latch and WR pin of the processor respectively. The processor is set to the mode of time-sharing multiplexing of the address bus and the data bus. In this way, the FPGA can latch the address of the processor through the ALE signal. The control command generator is used to decode and generate corresponding commands and operations. The DMA controller is a specific controller written by us. It needs to make DMA_EN valid when receiving the DMA enable command of the processor, and then start DMA to transfer data once after receiving the DMA start signal DMA_restart. Each time it is started, a page of 2K data is transmitted. During the transmission process, because it is a read of multiple FIFOs, in order to prevent the data from being messed up, we use a specific controller to match DMA_FLASH_WE and DMA_FIFO_RD of multiple FIFOs to unify them, resulting in a multi-chip FIFO rotation read operation.
In the design of sampling rate selection, we first use the software system of the microprocessor to give the hardware system of the FPGA a sampling rate selection value, and then the hardware system of the FPGA will decode the frequency value given by the microprocessor. The frequency selector will generate the corresponding frequency output according to this value, and the frequency output by the frequency selector will be input into the state machine controlling the AD conversion. In this way, the state machine controlling the AD conversion will perform corresponding frequency acquisition, data reading and data writing to the FIFO according to the input frequency.

3 Control and storage module
This system adopts pipeline operation mode when designing the storage mode. There are two stages in the writing of Nandflash memory: data loading stage (that is, writing data to the page data register through the I/O port) and programming stage (inside the chip, transferring the data in the page data register to the non-volatile storage unit). The data programming stage is automatic and does not require other operations of the external system, but it takes a long time, and its typical value is 200μs. If the pipeline storage method is used, the disadvantage of the slow writing speed of the Nandflash chip can be overcome. The principle of the writing operation process of the Nandflash memory using the pipeline operation method is shown in Figure 3. First, load the data to the first Nandflash. After the data is loaded, the first Nandflash will then enter the automatic data programming stage; then load the data to the second Nandflash. After the data is loaded, the second Nandflash will also enter the automatic data programming stage; then perform the same operations on the third Nandflash and the fourth Nandflash in turn. When the data of the fourth Nandflash is loaded, the first Nandflash has just finished automatically programming the data, and then repeat the loading and automatic programming of data stages at the beginning from the first Nandflash. This cycle continues until the data collection is completed. This is the storage method of the pipeline. From the overall time point of view, the entire system is constantly transmitting and storing data.

During data loading, this system applies DMA transfer control, that is, whenever the FIFO half-full flag signal HF generates a valid level, the processor starts an interrupt. In the interrupt program, the processor will complete the Nandflash write command and address, as well as the start of the DMA controller. Once the DMA controller is started, the processor will go to the background to perform effective address calculations and other operations without participating in the data transmission process. The entire data transmission process from FIFO to Nandilash memory is completed by the DMA controller written inside the FPGA. Start the DMA controller once to transfer a page of 2048 bytes of data, and one interrupt will complete the transfer of 16K bytes. The timing oscilloscope waveform of the DMA transfer is shown in Figure 4: Channels 0, 1, 2, and 3 are the FIFO read data timing waveforms, and channel 4 is the Nandflash write timing waveform. After a DMA transfer is completed, the processor must also determine whether the current page is the last page, page 64. If it is not the last page, the page address is increased by 1, and the DMA transfer sampling data operation continues. If the current page is the last page, page 64, determine whether the current block is the last block of this file. If it is not the last block, add 1 to the block address and compare it with the invalid block table to determine whether this block is a valid block. If it is, set the page address to 0 and continue the DMA transfer sampling data operation. If the current block is the last block of this file, the data acquisition operation of this file is completed, that is, this acquisition is completed.

4 Conclusions
The test results show that the acquisition system has stable performance and the acquisition speed can be maintained above 10 Mb/s, which meets the design requirements. The system has practical value for hardware design with low cost, high speed and reliability.