Design of a high-speed bit error tester based on FPGA

Abstract: The error code tester is an important device for detecting the reliability of communication systems. Traditional error code testers are based on the collaborative work of CPLD and CPU. They are not only complex in structure and expensive, but also inconvenient to carry. The high-speed error code tester based on FPGA uses FPGA to complete the integrated design of control and test modules, which improves the functional scalability and integration of the system, so that each functional module can be changed accordingly without changing the hardware circuit. The m sequence is sent as test data at the transmitting end, and its test rate can reach up to 155 MH/s. Since the functions of each protocol layer on the physical layer are concentrated in the internal implementation of FPGA, the design complexity of hardware and software is reduced, and the development cycle of the system is shortened, which has the characteristics of upgradeability.
Keywords: high-speed error code tester; field programmable gate array; Vetilog hardware description language; module primitive; simulation; M sequence code

As an ideal tool for acceptance, maintenance and fault query of digital communication systems, the error code analyzer is widely used in the monitoring of transmission quality of coaxial cables, optical fibers, satellites and inter-office relays that comply with CEPT (European Confence of Postal and Telecommunications Administrations) digital series communication systems. The index for evaluating the reliability of a communication system is to detect the size of the bit error rate of the communication system during data transmission. The high-speed signal bit error tester designed in this paper is used to detect the reliability of the receiving module that receives and sends burst optical signals in EPON. At present, the working modes of the bit error analyzer have developed into the following four types: analyzer mode, generator mode, analyzer/generator mode, and direct mode. The bit error tester in this design belongs to the third type, that is, the bit error tester can generate the test bit stream and perform bit error testing.
The bit error tester is mainly composed of several modules such as the sending module, the receiving module, the display module, and the control module. The system hardware structure block diagram is shown in Figure 1. The sending and receiving modules are implemented in FPGA, the control module is implemented by a single-chip microcomputer, and the display module is driven by a single-chip microcomputer. This makes the designed bit error analyzer have the characteristics of light size, rich interfaces, simple and easy to use, low cost, and upgradeable core.

1 Design of FPGA-based bit error tester
FPGA realizes the core functions of the bit error tester in this design. The FPGA design uses a top-down modular design method. The modules designed based on FPGA include: SY87739L frequency meter control module, SY87700 clock extraction control module, counting module, pseudo-random sequence sending module, data receiving module, and communication module with the single-chip microcomputer.
1.1 Control module of frequency synthesis chip SY87739L
In the design, the frequency synthesized by SY87739L is used for the synchronous clock of pseudo-random sequence synthesis, because the bit error tester can test 4 frequencies of 32 Mb/s, 64 Mb/s, 122 Mb/s, and 155 Mb/s. Therefore, the chip must synthesize the corresponding frequency according to the set parameters. Which one is synthesized is controlled by FPGA to realize the control of SY87739L.
SY87739L (Programmed transparent 3.3 V 10~729 MHz fractional-N synthesizer) is a frequency synthesis chip. According to a reference frequency source, it can synthesize differential frequencies in the range of 10 to 729 MHz. In addition, it can accurately synthesize the corresponding reference frequency for the standard transmission protocol. The frequency synthesized by SY87739L is determined by a 32-bit serial input programming data. When PROGCS is high, the programming data will be received by SY87739L. If the user needs to change the programming data to obtain a new frequency, PROGCS should be set to a high level first, and then fall back to a low level after a delay (waiting for the 32-bit programming data to be received by SY87739L). That is, at the falling edge of PROGCS, SY87739L will determine the synthesized new frequency based on the 32-bit programming data received in the previous period. The specific steps are as follows: 1) Determine the value of the programming data; 2) Set PROGCS to a high level; 3) Serially input 32-bit programming data (input from the PROGDI pin) and input the clock signal at the PROGSK end; 4) Set PROGCS to a low level; 5) Wait for LOCKED to jump to a high level.
According to the working principle of SY87739L, the control code of SY87739L can be written in hardware language. Figure 2 is the graphic element synthesized by Verilog code using Synplify Pro8.1.

The module controls SY87739L to synthesize 32M frequency function simulation results (simulated by ModelSim SE6.1) as shown in Figure 3.

In the test file, DATA-I is assigned a value of 00000001. It can be observed that the programming data outputted serially by prog_di is 0000_01100_01101_0100_000_10001_101_101; prog_cs is high level when prog_di outputs valid programming data, and falls back to low level after the programming data output is completed: PROGSK outputs the programming clock of SY87739L. After analysis, it can be seen that the SY87739L control module can achieve the expected function.
1.2 The control module of the clock extraction chip SY87700V
SY87700V extracts the clock and recovers the data received by FPGA. The recovered data is compared with the local pseudo-random sequence generated by the receiving end to realize error detection. When comparing the two data streams, the extracted clock is used as the synchronization clock. Before extracting data, SY87700V needs to know the range of the extracted frequency in advance, and this frequency range is sent to SY87700V by FPGA. Whether the reference clock of SY87700V is divided or not is also controlled by FPGA according to the set parameters. In addition, this module also needs to realize the function of FPGA reading SY87700V to determine whether SY87700V has completed clock extraction and data recovery. According to the working principle of SY87700V, the hardware language Verilog can be used to write a program to realize the module of controlling SY87700V in FPGA. Figure 4 is the graphic element synthesized by the code.

The result waveform of the functional simulation of SY87700V controlled by FPGA to extract clock and recover data from 122M data (simulated by Modelsim) is shown in Figure 5 below.

In the test file, data_i is assigned a value of 000011111. It can be observed that FREQUSEL1 outputs a value of 1, FREQUSEL2 outputs a value of 0, FREQUSEL3 outputs a value of 1, DIVSEL1 outputs a value of 0, and DIVSEL2 outputs a value of 1. CLKSEL outputs a high level (this signal can control SY87700V to complete the function of extracting the input data clock). CD also outputs a high level (enabling SY87700V to perform data recovery and clock extraction normally). It can be seen from the figure that the signal output by the SY87700V control module can control SY87700V to complete the clock extraction and data recovery of 122M data, and realize the expected logical function.
1.3 Counting module
The counting module is used to calculate the total number of codes, the number of bit errors, and the number of bit error blocks. The counter is a synchronous reset counter. The primitive synthesized from the Verilog HDL code is shown in Figure 6.

The maximum count value of the counting module is 252. The result of functional simulation of the counting module using Modelsim simulation software is shown in Figure 7:

In the test file, c_i is assigned a pulse stream, and the counting result output in cnt_o is correct. The correctness of the function of this module can be judged.
1.4 Pseudo-random sequence transmission module
The task of the pseudo-random sequence transmission module is to generate a pseudo-random sequence with the frequency synthesized by SY87739L as the clock and output the pseudo-random sequence in series. This module can generate three levels of pseudo-random sequences, and the generated pseudo-random sequences are output in series. The specific number of synthesized levels depends on the control signal output by the washbone module (the communication control module between FPGA and single-chip microcomputer): P09T-en (synthesized 9-level m-sequence enable signal), P15T-en (synthesized 15-level m-sequence enable signal), P23T-en (synthesized 23-level m-sequence enable signal). Which of the three signals is high level synthesizes the corresponding level of pseudo-random sequence. The primitive synthesized by Verilog HDL code is shown in Figure 8.

The functional simulation results (synthesizing a 23-level pseudo-random sequence) are shown in FIG9 .

In the test file, the corresponding value of the input signal of the module is assigned to complete the function of synthesizing a 23-level pseudo-random sequence. In the figure above, ser_o serially outputs a 23-level m-sequence, which can be judged that the module can successfully synthesize the m-sequence to realize the function of the error tester transmitter.
1.5 Data receiving module
The functions realized by the receiving module in FPGA are: 1) m-sequence generation, 2) error detection. The logical function of the former is similar to that of the transmitting module, and its role is to generate a local m-sequence with the same code shape as the transmitting end and bit alignment; the role of the latter is to compare the received data with the local m-sequence to detect whether there is an error. If there is an error, an error pulse is output to the counting module for statistics. This module can receive three levels of pseudo-random sequences, and the primitives synthesized by the Verilog program are shown in Figure 10.

When the test code sent is an m-sequence with a period of 29-1, the simulation waveform of the data receiving module is shown in FIG11 .

In the simulation file, a code stream is assigned to the module input port ser_i. When the assigned code stream is synchronized with the local pseudo-random sequence (same frequency and same phase), the data receiving module outputs a high level at the sum_o port every time it compares a bit code. If there is a bit error during the comparison, the prt_o port outputs a high level. In the figure above, PRBS_r is a locally synthesized pseudo-random sequence. It can be seen that the module can realize the generation of m-sequences and the detection and statistics of bit errors.

1.6 FPGA and MCU communication control module
The functions of the FPGA and MCU communication control module (washbone module) are: 1) Control FPGA to send data (total number of bits, number of bit errors, number of error blocks) to the data line; 2) Control FPGA to receive control data sent by the MCU to the data line. The FPGA and MCU communication control module generates signals to control other modules from the control information received by FPGA. These control signals include the enable signal of SY87739L frequency synthesis, the enable signal of SY87700V control module, the counter reset signal, the level and rate of pseudo-random code, and the control signal of the sending and receiving interface. The primitives synthesized from the source program are shown in Figure 12.

When the data frequency extracted by SY87700V is 30.72 MHz, the reference frequency of SY87700V is 3.84 MHz. Figure 13 shows the functional simulation results of the communication control module between FPGA and MCU. This simulation is a simulation of the function of controlling FPGA to receive MCU control data in the washbone module. In the test file, the communication data signal between FPGA and MCU is assigned as 0001010 (controlling the module to generate P09T_en, mb_OO_en, mb_OI_en as high-level signals); exchange is assigned as high-level, that is, FPGA stores data (total number of bits, number of bit errors, number of bit error blocks) into the internal storage unit of FPGA; FPGA GSn=0. WRn=1, that is, FPGA reads the data on the data line and stores it in the internal register memory. Among the output pins of this module: P09T_en, mb_OO_en, mb_OI_en output high level, which controls the pseudo-random sending module to synthesize 9-level m sequence, and the sending and receiving port types are both optical interface types. From the following simulation diagram, it can be judged that this module can realize the required logical functions.

2 Synthesis results of each module
2.1 Synthesis report
Synthesis optimization (SynthesisIlesize) refers to translating design inputs such as HDL language and schematics into logical connections (netlists) composed of basic logic units such as AND, OR, NOT gates, RAM, and registers, and optimizing the generated logical connections according to the goals and requirements (constraints), and outputting edf and edn files for implementation by the FPGA manufacturer's layout and routing.
In this design, the synthesis tool Synplify Pro8.1 is used for synthesis. The results synthesized by this synthesis tool occupy a small area, have a high operating frequency, and a fast synthesis speed. It is one of the most popular and efficient synthesis tools in FPGA technology. Each module in the FPGA is synthesized by the synthesis tool Synplify Pro8.1. Before synthesis, the divider clock with a division factor of 100 is constrained to 10.0MHz in the timing constraint file; the synchronous clock CDR00TKP of the synthesized m-sequence in the receiving module is constrained to 125.0 MHz; the CDRK input is the clock generated by the 7.68 MHz crystal oscillator. According to the rate of the synthesized m-sequence, the FPGA determines whether CDRK is divided by two. The FPGA uses the processed CDRK as the reference clock for the clock extraction chip. The clock constraint is 7.68 MHz;
DDS39REFCLK is the reference clock of the clock synthesis module, and the clock constraint is 30MHz: DDS39TKP input is the synthesized clock of the clock synthesis chip SY87739L, which is used to generate the synchronous clock of the m-sequence in the sending module, and the DDS39TKP constraint is 95 MHz.
It can be seen from the synthesis report that the synthesis results of each clock after synthesis exceed the constrained frequency and meet the timing requirements. In addition, the resource utilization in the FPGA can be obtained from the report: 59 I/O primitive resources are used, and 0 I/O registers are used. 775 non-I/O registers are used, accounting for 50% of the total FPGA resources. The total logic resources used are 1,253 lookup tables, accounting for 81% of the total resources.
2.2 RTL (register level) view
The RTL view is a logical connection diagram composed of basic logic units such as AND, OR, NOT gates, RAM, and registers. From it, we can get the connection status of each module in the FPGA and judge whether the system written in the hardware description language is logically correct. Figure 14 is the RTL view synthesized by Synplify.

By analyzing the connection of each module in the figure above, it can be judged that the program written by Verilog is correct in the logical connection design of each module, and the synthesized edf file can be sent to the Xinlinx layout and routing device for implementation.

3 Conclusion
The content of this paper is a bit error tester used in high-speed communication systems. This high-speed signal bit error tester is designed based on FPGA (field programmable gate array) as the core, and is suitable for disconnection bit error detection. The bit error tester sends m sequence as test data at the transmitting end, and its test rate can reach up to 155Mbps. With the rapid development of high-speed digital circuits today, the test rate of this bit error tester can be further improved, but once the working rate of the bit error tester is improved, it is impossible to avoid the problems that need to be paid attention to in the design of high-speed digital circuits, such as signal integrity and electromagnetic interference in high-speed digital circuits. Since the core functions of the bit error tester are implemented using FPGA, the system has the characteristics of being upgradeable.
The software part of the design uses Verilog hardware language to write programs. The software development environment uses several software such as Xflinx's EDA integrated development tool ISE8.1, simulation tool ModelSim SE 6.1b, and synthesis tool SynplifyPro8.1. The hardware implementation uses the XC2S50E platform-level FPGA in Xilinx's SPARTANHE series as the core functional chip. The design of the sending part, receiving part and bit error statistics module of the bit error tester is realized in FPGA. With the help of the clock synthesis chip Micrel SY87739L, the clock extraction chip Micrel SY87700V and the control of the single-chip microcomputer (C8051F010), the whole system is small in size and low in cost.