The three most common analog-to-digital converter types in analog front-ends are successive approximation (a), pipeline (b), and delta-sigma (c).
The following block diagrams describe these different architectural concepts in a very simple way.
a. In the successive approximation analog-to-digital converter, the analog input voltage is "frozen" through sample and hold technology. Then, the N-bit register is set to mid-amplitude mode: the highest bit of the register is set to 1, allowing the digital-to-analog converter output to reach mid-range values.
If the input voltage is higher than the digital-to-analog converter output voltage, the comparator output is true and the highest bit is still 1. But if the input voltage is lower than the digital-to-analog converter output voltage, the highest bit of the register will become logic 0.
The converter control logic will move to the next bit, causing it to increase and perform another comparison until the lowest bit is reached. When the conversion is complete, the N-digit number will appear in the register. See related illustrations
figure 1
b. In a pipelined analog-to-digital converter, each parallel stage performs one-bit sequential sampling or multiple-bit sequential sampling simultaneously. The analog input is suitable for sample and hold, and a first-order analog-to-digital converter converts it to 3 bits. This is then fed into a small digital-to-analog converter that produces an analog output from the sample-and-hold output value. The "residual signal" is amplified and then fed into the next stage, and so on. The shift register adjusts the bit values of each order in time and passes the combined samples to the error correction logic. See related illustrations
figure 2
c. The Δ-Σ converter is not simply used for direct time domain analysis, but is often used for frequency domain analysis. (A detailed mathematical analysis is described in Intersil Applications Note 9504 at www.intersil.com/data/an/an9504.pdf.) One can say that the input signal is roughly oversampled (sampling target well above the Nyquist value, In order to get the maximum attention to the input frequency band), aliasing can be eliminated. More importantly, it spreads the frequency components of quantization noise (resolution errors caused by turning a continuous input signal into a series of discontinuous signals) over a larger bandwidth. This reduces the average level of quantization noise and increases the frequency of most noise. Most noise can be eliminated by sharply attenuating the frequency band of interest with a digital filter. See related illustrations
image 3
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