Electromagnetic Compatibility (EMC) Design of Hybrid Integrated Circuits

1 Introduction

Hybrid integrated circuit (HIC) is an integrated circuit made by combining semiconductor integration technology with thick (thin) film technology. Hybrid integrated circuits are made by using film forming methods on substrates to make thick film or thin film components and their interconnection lines, and by mixing and assembling discrete semiconductor chips, monolithic integrated circuits or micro components on the same substrate, and then encapsulating them. It has the characteristics of high assembly density, high reliability, and good electrical performance.

As the size of circuit boards decreases, wiring density increases, and operating frequencies continue to increase, electromagnetic interference in circuits becomes more and more prominent, and electromagnetic compatibility issues become the key to whether an electronic system can work properly. The electromagnetic compatibility design of circuit boards becomes the key to system design.

2 Electromagnetic compatibility principle

Electromagnetic compatibility refers to the ability of electronic equipment and power supplies to work normally and reliably in a certain electromagnetic interference environment. It also refers to the ability of electronic equipment and power supplies to limit their own electromagnetic interference and avoid interfering with other surrounding electronic equipment.

The occurrence of any electromagnetic interference must meet three basic conditions: first, there must be an interference source, that is, a device or equipment that generates a harmful electromagnetic field; second, there must be a way to propagate the interference, which is generally believed to have two ways: conduction coupling and radiation coupling; third, there must be sensitive equipment that is susceptible to interference. Therefore, solving electromagnetic compatibility problems should target the three elements of electromagnetic interference and solve them one by one: reduce the interference intensity of the interference-generating components; cut off the propagation path of the interference; and reduce the system's sensitivity to interference.

The electromagnetic interference existing in the design of hybrid integrated circuits includes: conducted interference, crosstalk interference and radiated interference. When solving EMI problems, we should first determine whether the coupling path of the emission source is conducted, radiated, or crosstalk. If a high-amplitude transient current or a rapidly rising voltage appears near a conductor carrying a signal, the electromagnetic interference problem is mainly crosstalk. If there is a complete circuit connection between the interference source and the sensitive device, it is conducted interference. Radiated interference will occur between two parallel wires transmitting high-frequency signals.

3. Electromagnetic compatibility design

When designing the electromagnetic compatibility of hybrid integrated circuits, the first thing to do is to do functional testing. In the circuit that has been determined, check whether the electromagnetic compatibility indicators can meet the requirements. If not, modify the parameters to meet the indicators, such as transmission power, operating frequency, and reselect devices. The second is to do protective design, including filtering, shielding, grounding and overlapping design. The third is to do layout adjustment design, including overall layout inspection, layout inspection of components and wires, etc. Usually, the electromagnetic compatibility design of the circuit includes: selection of processes and components, circuit layout and wiring layout, etc.

3.1 Selection of process and components

There are three manufacturing processes for hybrid integrated circuits: single-layer thin film, multi-layer thick film, and multi-layer co-fired thick film. The thin film process can produce small-size, low-power, and high-current density components required for high-density hybrid circuits. It has the characteristics of high quality, stability, reliability, and flexibility, and is suitable for high-speed, high-frequency, and high-packaging-density circuits. However, it can only do single-layer wiring and the cost is relatively high. The multi-layer thick film process can manufacture multi-layer interconnected circuits at a lower cost. From the perspective of electromagnetic compatibility, multi-layer wiring can reduce the electromagnetic radiation of the circuit board and improve the anti-interference ability of the circuit board. Because a dedicated power layer and ground layer can be set up, the distance between the signal and the ground line is only the distance between the layers. In this way, the loop area of ​​all signals on the board can be minimized, thereby effectively reducing differential mode radiation.

Among them, the multi-layer co-fired thick film process has more advantages and is the mainstream technology for passive integration. It can realize more layers of wiring, is easy to embed components, improve assembly density, and has good high-frequency characteristics and high-speed transmission characteristics. In addition, it has good compatibility with thin film technology. The combination of the two can achieve hybrid multi-layer circuits with higher assembly density and better performance.

Active devices in hybrid circuits generally use bare chips. If bare chips are not available, corresponding packaged chips can be used. To obtain the best EMC characteristics, surface-mount chips should be used as much as possible. When selecting chips, low-speed clocks should be used as much as possible on the premise of meeting product technical indicators. Never use AC when HC can be used, and do not use HC if CMOS4000 can be used. Capacitors should have low equivalent series resistance to avoid large attenuation of the signal.

The packaging of the hybrid circuit can use a base and shell cover made of Kovar metal, with parallel seam welding, which has a good shielding effect.

3.2 Circuit Layout

When laying out a hybrid microcircuit, three main factors must be considered: the number of input/output pins, device density, and power consumption. A practical rule is that the chip component occupies 20% of the substrate area and dissipates no more than 2W per square inch.

In terms of device layout, in principle, related devices should be placed as close as possible, digital circuits, analog circuits and power circuits should be placed separately, and high-frequency circuits should be separated from low-frequency circuits. Devices that are prone to noise, low-current circuits, high-current circuits, etc. should be kept as far away from logic circuits as possible. Major interference and radiation sources such as clock circuits and high-frequency circuits should be arranged separately and away from sensitive circuits. Input and output chips should be located close to the I/O exit of the hybrid circuit package.

The high-frequency components should be connected as short as possible to reduce the distributed parameters and electromagnetic interference between each other. The components susceptible to interference should not be too close to each other, and the input and output should be as far away as possible. The oscillator should be as close as possible to the location where the clock chip is used, and away from the signal interface and low-level signal chip. The components should be parallel or perpendicular to one side of the substrate, and the components should be arranged in parallel as much as possible. This will not only reduce the distributed parameters between the components, but also conform to the manufacturing process of the hybrid circuit and be easy to produce.

The power and ground lead pads on the hybrid circuit substrate should be arranged symmetrically, and it is best to evenly distribute many power and ground I/O connections. The mounting area of ​​the bare chip is connected to the most negative potential plane.

When multi-layer hybrid circuits are used, the arrangement of the layers of the circuit board changes with the specific circuit, but generally has the following characteristics.

(1) The power supply and ground layer are distributed in the inner layer, which can be regarded as a shielding layer. It can effectively suppress the common-mode RF interference inherent in the circuit board and reduce the distributed impedance of the high-frequency power supply.

(2) The power plane and ground plane in the board should be as close to each other as possible. Generally, the ground plane is above the power plane. In this way, the interlayer capacitance can be used as a smoothing capacitor for the power supply. At the same time, the ground plane can shield the radiation current distributed on the power plane.

(3) The wiring layer should be arranged as close to the power or ground plane as possible to produce a flux cancellation effect.

3.3 Wire layout

In circuit design, people often only focus on improving wiring density or pursuing uniform layout, ignoring the impact of line layout on preventing interference, causing a large number of signals to radiate into space to form interference, which may lead to more electromagnetic compatibility problems. Therefore, good wiring is the key to determining the success of the design.

3.3.1 Ground Wire Layout

The ground wire is not only the potential reference point for the circuit, but also a low impedance loop for the signal. The most common interference on the ground wire is the ground loop interference caused by the ground loop current. Solving this kind of interference problem is equivalent to solving most of the electromagnetic compatibility problems. The noise on the ground wire mainly affects the ground level of the digital circuit, and when the digital circuit outputs a low level, it is more sensitive to the noise of the ground wire. The interference on the ground wire may not only cause the circuit to malfunction, but also cause conducted and radiated emissions. Therefore, the key to reducing these interferences is to reduce the impedance of the ground wire as much as possible (for digital circuits, reducing the ground wire inductance is particularly important).

The following points should be noted when laying out the ground wire:

(1) According to different power supply voltages, ground wires are set separately for digital circuits and analog circuits.

(2) The common ground wire should be as thick as possible. When using multi-layer thick film technology, a special ground plane can be set up, which helps to reduce the loop area, but also reduces the efficiency of the receiving antenna. It can also serve as a shield for the signal line.

(3) Comb-shaped ground lines should be avoided. This structure makes the signal return loop very large, which will increase radiation and sensitivity, and the common impedance between chips may also cause circuit malfunction.

(4) When multiple chips are installed on the board, a large potential difference will appear on the ground line. The ground line should be designed as a closed loop to improve the noise tolerance of the circuit.

(5) For circuit boards with both analog and digital functions, the analog ground and digital ground are usually separated and connected only at the power supply.

3.3.2 Layout of power lines

Generally speaking, in addition to interference caused directly by electromagnetic radiation, electromagnetic interference caused by power lines is the most common. Therefore, the layout of power lines is also very important, and the following rules should usually be followed.

(1) The power line should be as close to the ground line as possible to reduce the area of ​​the power supply loop, which will reduce differential mode radiation and help reduce circuit crosstalk. The power supply loops of different power supplies should not overlap with each other.

(2) When using multi-layer technology, separate the analog power supply and the digital power supply to avoid mutual interference. Do not overlap the digital power supply and the analog power supply, otherwise coupling capacitance will be generated, destroying the separation.

(3) The power plane and the ground plane can be completely isolated by dielectrics. When the frequency and speed are very high, a dielectric slurry with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged under the ground plane to shield the radiation current distributed on the power plane.

(4) The power pin and ground pin of the chip should be decoupled. The decoupling capacitor should be a 0.01uF chip capacitor and should be installed close to the chip to minimize the loop area of ​​the decoupling capacitor.

(5) When selecting a surface-mount chip, try to choose a chip with the power pin and ground pin close to each other. This can further reduce the power supply loop area of ​​the decoupling capacitor and help achieve electromagnetic compatibility.

3.3.3 Layout of signal lines

When using a single-layer film process, a simple and applicable method is to lay out the ground wire first, then place key signals, such as high-speed clock signals or sensitive circuits close to their ground loops, and finally lay out other circuits. It is best to arrange the signal lines according to the flow order of the signal to make the signal flow smoothly on the circuit board.

To minimize EMI, keep the signal line as close as possible to the return signal line it forms, and make the loop area as small as possible to avoid radiation interference. Low-level signal channels cannot be close to high-level signal channels and unfiltered power lines, and noise-sensitive wiring should not be parallel to high-current and high-speed switching lines. If possible, lay out all key traces in strip lines. Incompatible signal lines (digital and analog, high speed and low speed, high current and low current, high voltage and low voltage, etc.) should be kept away from each other and not run parallel. Crosstalk between signals is extremely sensitive to the length and spacing of adjacent parallel traces, so try to increase the spacing between high-speed signal lines and other parallel signal lines and reduce the parallel length.

The inductance is proportional to its length and the logarithm of its length, and inversely proportional to the logarithm of its width. Therefore, the conduction strip should be as short as possible, and the length of each address line or data line of the same component should be kept consistent as much as possible. The wires used as circuit input and output should avoid being parallel to each other as much as possible. It is best to add a ground wire in between to effectively suppress crosstalk. The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.

In the thick film process, in addition to complying with the rules of single-layer wiring, you should also pay attention to:

Design a separate ground plane, and arrange the signal layer adjacent to the ground layer. When it cannot be used, a ground line must be set near the high-frequency or sensitive circuit. The signal lines distributed on different layers should be perpendicular to each other, so as to reduce the electric and magnetic field coupling interference between the lines; the signal lines on the same layer should maintain a certain distance, and it is best to isolate them with the corresponding ground line loop to reduce the signal crosstalk between the lines. Each high-speed signal line should be limited to the same layer. The signal line should not be too close to the edge of the substrate, otherwise it will cause the characteristic impedance to change, and it is easy to generate fringe fields, increasing outward radiation.

3.3.4 Clock Line Layout

Clock circuits play an important role in digital circuits and are also the main source of electromagnetic radiation. The spectrum of radiation energy of a clock signal with a 2ns rising edge can reach 160MHz. Therefore, designing a good clock circuit is the key to ensuring electromagnetic compatibility of the entire circuit. Regarding the layout of the clock circuit, there are the following precautions:

(1) Do not use a daisy-chain structure to transmit clock signals. Instead, use a star structure, where all clock loads are directly connected to the clock power driver.

(2) All conduction bands connecting the crystal oscillator input/output terminals should be as short as possible to reduce the impact of noise interference and distributed capacitance on the crystal oscillator.

(3) The ground line of the crystal capacitor should be connected to the device using a conductor strip that is as wide and short as possible; the digital ground pin closest to the crystal should have as few vias as possible.

4 Conclusion

The article elaborates on the causes of electromagnetic interference in hybrid integrated circuits, and proposes the issues that should be paid attention to and specific measures to be taken in the design of system electromagnetic compatibility in combination with the process characteristics of hybrid integrated circuits, laying a foundation for improving the electromagnetic compatibility of hybrid integrated circuits.
The article's innovation: Starting from improving the electromagnetic compatibility of the system, combined with the process characteristics of hybrid integrated circuits, it proposes the issues that should be paid attention to and specific measures to be taken in the design of hybrid integrated circuits.