Design of a high-speed real-time digital beamformer

0 Introduction

Radar, as a special radio equipment, must follow the development path from analog to digital and then to software. Digital beamforming technology is regarded as a technology that must be adopted by the new generation of radar. It retains all the information of the antenna array unit signal and can use advanced digital signal processing technology to process the array signal, which can obtain excellent beam performance, easily obtain super-resolution and low sidelobe performance, and realize beam scanning, self-calibration and adaptive beamforming. It is precisely because of the above characteristics that the successful application of DBF technology will have a significant impact on the development of modern radar technology.

In the engineering process of digital beamforming technology, some problems were also encountered. They mainly include: the amount of data transmission is too large, especially when the number of array elements is large, which limits the increase of channels; the amount of calculation for the estimation of the direction of the incoming wave and the update of the weight is too large, which makes the weight update speed relatively slow and cannot be used on some high-speed moving carriers; when the number of arrays is large, the complex multiplication operation of the high-speed real-time beamformer consumes more resources, especially when multiple beams need to be formed. The original DBF system encountered a data transmission bottleneck problem. The sampling data can only be transmitted through the PCI bus, and it cannot guarantee that the data of all channels are transmitted in real time. Therefore, it can only do direction finding work with less data requirements, and cannot do real-time beamforming. In order to overcome these difficulties, the direction finding data and beamforming data are transmitted separately here, and the LVDS technology is used to solve the multi-channel high-speed data transmission. The high-density FPGA with built-in high-performance DSP core is selected to parallelly implement a large number of complex multiplication operations in beamforming.

1 DBF system composition

The DBF system includes array receiving antenna, multi-channel receiver, multi-channel data acquisition board, FPGA beamforming board, DSP weight calculation board, external clock trigger module, industrial computer and other units, as shown in Figure 1. The receiver generally adopts superheterodyne method to realize down-conversion and filtering of array receiving signal, and amplify the signal to the level required for A/D conversion. The most important function of DBF system is to realize the estimation of incoming wave direction (direction finding) and beam forming. The DSP weight calculation board is responsible for the estimation of incoming wave direction and weight calculation tasks. The weight calculation should be based on the direction finding results and beam scanning, as well as the requirements of anti-interference. The FPGA beamforming board is responsible for the whole array beamforming task. According to the weight calculation results, the beamformer forms the required receiving digital beam by performing complex weighted operations on the digital array unit receiving signal.

In this system, four four-channel acquisition boards ICS554 realize the analog/digital conversion and digital down-conversion of the intermediate frequency signal of 16 array elements. In order to achieve synchronization of all channels, the acquisition boards all work in the external signal trigger mode, and the external sampling clock is completely synchronized; the incoming wave direction estimation and weight update calculation are completed by the DSP weight calculation board. The amount of data required for each channel for calculation is usually not large. ICS554 transmits the required data for direction finding to the DSP weight calculation board through the PCI bus; the FPGA beamforming board needs to perform complex weighted summation of the data of each channel to obtain the final required beam in order to realize the beamforming of the entire array, so a large amount of data needs to be transmitted. The four ICS554 transmit high-speed data to the FPGA beamforming board through LVDS; after the weight is calculated by the DSP weight calculation board, it is sent to the FPGA beamforming board through a custom serial port communication.

2 Real-time digital beamformer design

2.1 High-speed data acquisition and transmission

In this system, due to the wide signal bandwidth, the ICS company's four-channel acquisition board ICS554 is selected to implement the data acquisition task. ICS554 is an integrated product of ADC and digital down conversion (DDC). ADC determines the dynamic range of the system, which increases by 6 dB per bit according to the number of bits K of the ADC and increases with the number of parallel receiving channels N expressed in dB. The composition of ICS554 is shown in Figure 2. It mainly includes 4 independent 14 b/105 MHz analog/digital converters AD6645, 4 orthogonal down converters (QDDC) GC4016, 1 1 million gate user-programmable FPGA (Xilinx XC2V1000), 2 512 KB FIFOs and 1 PCI interface chip QC5064. Among them, the input signal bandwidth of AD6645 can reach 50kHz～200 MHz, and the maximum false-free dynamic range (SFDR) is 92 dB (10 MHz±50 kHz). Each GC4016 includes 4 independent DDC channels, each channel can independently control its local oscillator frequency and initial phase, and the frequency resolution is better than 24 MHz. The full-band coverage allows each GC4016 to share a common RF front end and A/D converter. The large-capacity FIFO is used to buffer the output data, and the FPGA can be used to perform preliminary processing on the output signal. ICS554 has high stability, excellent nonlinearity and orthogonality and other system characteristics, and is relatively flexible. The programmable control parameters of ICS554 are completed by configuring different registers.

The system has 16 antenna units, with an A/D sampling frequency of 105 MHz. After digital down-conversion, two 24-bit data streams of 30 MHz I and Q are formed. If all data are transmitted to the back-end FPGA beamforming board for processing, the amount of data that each ICS554 acquisition board needs to transmit per second is:

4×2×24×30 Mb/s=5.625 Gb/s

Considering that the acquisition board ICS554 does not provide a higher performance data transmission bus, it is difficult to achieve data transmission at a flow rate of 5.625 Gb/s. Therefore, the FPGA resources reserved for users on the board are used to perform a sub-array beam synthesis in the acquisition board, and the I and Q data of the four channels of the same acquisition board are weighted and summed to obtain the synthesized I and Q data, and the data flow rate is reduced to 1440 Mb/s.
The connection between the acquisition board ICS554 and the FPGA beamforming board adopts LVDS technology. Low Voltage Differential Signaling (LVDS) is a technology that uses low-swing differential voltage to transmit signals serially. This signal can be transmitted at a rate of hundreds of Mb/s or even Gh/s on differential PCB wire pairs or balanced cables. It has the advantages of low voltage, low radiation, low power consumption, low cost, strong anti-interference ability and built-in clock, and is especially suitable for high-speed data transmission between devices with transmission distance requirements. However, LVDS only defines the signal electrical specifications. As a complete data communication specification, it also requires corresponding data transmission control. In order to improve efficiency, data without frame structure is directly transmitted. At the same time, in order to maximize the data transmission channels, the control signal between the sender and the receiver is cancelled, and a discontinuous sender clock is used. The send clock is given only when the sender data is valid. In this case, the receiver can use a continuous clock higher than the send clock to sample the send clock to determine whether the data is valid.

The acquisition board ICS554 itself has 64 general I/O ports reserved for users, which can be configured as LVDS I/O ports, which can improve data transmission capacity and anti-interference performance. The data transmission process is shown in Figure 3. The FPGA inside ICS554 first converts the 24b I, Q data stream into parallel/serial. It is easy to implement parallel/serial conversion with the state machine of VHDL language. Then the LVDS transmission module converts the LVTTL signal into LVDS signal for transmission. The receiving end FPGA beamforming board first converts the received LVDS signal into LVTTL signal, then synchronizes the data, and then converts the serial code into 24b I, Q data through serial/parallel conversion. Since the general I/O port provided to users by ICS554 is configured as an LVDS differential pair, the phase and mutual coupling of the differential pair are not well considered, and a dedicated balanced cable connection cannot be used. Therefore, the transmission rate must be reduced to reduce the transmission bit error rate and enhance reliability. At the same time, considering the configuration of a 9-bit LVDS port, 8-bit parallel transmission data, and 1-bit transmission clock signal, the LVDS transmission rate is:

30×2×24／8=180 Mb／s

The actual test also shows that the LVDS differential pair can work reliably at a transmission speed of 180 Mb/s, and the FPGA beamforming board can correctly receive the data from the acquisition board ICS554.

2.2 Real-time beamforming calculation

As mentioned above, the entire real-time beamforming is divided into two steps. First, the sub-array beamforming is completed in the acquisition board ICS554, and then the full-array beamforming is implemented in the FPGA beamforming board. How to ensure the real-time performance of the entire calculation is the key.

Beam formation is actually the amplitude and phase weighting of the digital signal after A/D conversion. The characteristics of the beam, such as beam pointing, sidelobe level, main lobe width, etc., are completely determined by the weights. The weight calculation mainly considers two factors. First, the amplitude and phase of each channel must be calibrated to overcome the influence of inconsistency and mutual coupling of each channel, and then spatial filtering is implemented to achieve the desired beam pointing. First, the amplitude and phase are calibrated. For the i-th unit:

Where: δφi, △ai are the phase difference and amplitude ratio between the ith channel and the standard channel respectively. If spatial filtering is to be achieved, it is necessary to add array factors to weight the amplitude and phase.

Where: φi is the phase weighting value of the i-th channel; αi is the amplitude weighting value. Different amplitude weighting forms can be flexibly selected according to different beam performance requirements (main lobe width, side lobe level, null position), and different αi will be obtained, and the weight matrix W will also be different. The weight update calculation is completed by the DSP processing board.

The initial subarray beamforming needs to realize the beamforming of four-channel units, that is, the complex weighted summation of the four intermediate frequency digital I and Q signals:

Where: Iout, Qout are the I and Q output results after 4-channel beamforming; ωir, ωii are the real and imaginary parts of the weight of the ith unit respectively. Since the sampling frequency of ICS554 is relatively high and there are many remaining available resources in the FPGA chip, parallel complex multiplication operation is adopted here, and 4 independent complex multiplication operation units are mapped using ISE software IP core design. The VHDL program design in the chip is shown in Figure 4.

Four acquisition boards ICS554 are used to independently perform sub-array beamforming, and then the results Iout and Qout are output to the FPGA beamforming board for complex summation, and finally the full array synthetic beam of 16 antenna units is obtained. Considering the complexity of FPGA operation, the XC3SD3400A chip of Xilinx with a built-in DSP core is selected. This chip has a very high cost performance. The built-in DSP core XtremeDSP DSP48A can achieve an operation speed of 250 MHz and a differential I/O transmission rate of 622 Mb/s. To ensure the real-time performance of the entire beamforming operation, the acquisition board sub-array beamforming operation, data transmission, and FPGA board full array beamforming operation are tested and analyzed in three aspects. The full array beamforming operation mainly performs complex addition operations in the XC3SD3400A, and the addition operation can reach up to 250 MHz, which is much higher than the data flow speed after digital down-conversion. The sub-array beamforming operation is to perform four-channel parallel complex multiplication and complex addition operations in the XC2V1000. The on-chip complex multiplication pipeline and complex addition operation clock frequency can reach 420 MHz. In fact, the computing power of sub-array and full-array beamforming is sufficient. The main bottleneck of the entire system is data transmission. The data transmission flow is large and the data transmission I/O port width is up to 8 bits. In the data transmission link, the low-speed multi-bit parallel data is converted into 250 MHz high-speed serial data using a multiplied clock; at the receiving end, the low-speed parallel data can be obtained by using a shift register to realize serial/parallel conversion. Simulation and actual tests also show that the real-time performance of the beamforming operation of the entire system can be guaranteed.

3 Conclusion

The high-speed real-time beamformer designed here improves the original DBF system. It can not only complete the direction finding work, but also realize high-speed data transmission and real-time digital beamforming of the whole array. The system is built on the acquisition board ICS554. Although ICS554 is a high-performance 4-channel acquisition board, it is expensive and only provides PCI interface. It does not provide other high-performance data transmission interfaces. When the number of array elements is more, its scalability is not strong. In order to meet the requirements of data transmission capacity, multiple groups of LVDS differential pairs are used for data transmission. Although the required speed is achieved, there are too many connecting cables, the mutual coupling effect is large, and the transmission distance is short. Therefore, in the subsequent system design, FPGA integration of faster high-speed serial differential RocketIO channels, optical fiber transmission and other technologies are used to improve performance and improve system scalability.