Design and implementation of RS485 interface error code tester based on FPGA

In digital communication, the bit error rate (BER) is an important indicator for measuring the quality of communication systems. Whether it is equipment failure, propagation fading, inter-code interference, adjacent channel interference, etc., all factors may cause system performance to deteriorate or even cause communication interruption, and the results can be expressed in the form of bit errors [1]. Therefore, the bit error tester is one of the main test instruments for modern communication systems.
At present, the commonly used traditional bit error tester has the advantages of rich test content and intuitive test results. However, due to the increasing complexity of communication systems, the diverse interface forms and the application of some non-standard bit rates, the use of traditional bit error testers is subject to certain restrictions. On the other hand, FPGA technology has developed rapidly in recent years. Using FPGA to design circuits has great flexibility, which can greatly improve the integration and design speed, and can also simplify the interface and control, which is conducive to improving the overall performance and working reliability of the system. This paper introduces the design and implementation of an RS485 interface bit error tester based on FPGA. The design has the characteristics of simple system, reliable function, unique interface, etc., and adds the function of measuring system transmission delay that traditional bit error testers do not have.
1 Design Background
The bit error tester designed in this paper is mainly used to test the bit error performance of a communication system. The communication system is a large and complex system. This paper mainly introduces the channel part, including the baseband channel encoding and decoding and the wireless channel transmission and reception. Its basic block diagram is shown in Figure 1.

In order to ensure good anti-interference ability in line transmission, the system uses RS485 interface and selects a bit rate of 4.096 Mb/s. Therefore, in order to test the bit error performance of the system shown in Figure 1, the bit error tester must have the following indicators:
(1) Logical interface: RS485 differential signal.
(2) Physical interface: DB9.
(3) Bit rate: 4.096 Mb/s.
Traditional bit error testers usually do not have the above three indicators. The bit error tester designed in this paper meets the above three indicators.
2 Bit error test principle
There are many forms of schemes to constitute a bit error tester. Its basic working process can be summarized as the following steps:
(1) Generate a code pattern that is the same as the transmitted code group in some way, and use the local code group with the same phase as the comparison standard.
(2) Compare the local code group with the received code group one by one, and output the bit error pulse signal.
(3) Count the bit error pulse signal and give the corresponding bit error rate.
In communication engineering applications, in order to simulate the statistical characteristics of data streams in real communications to the greatest extent, binary pseudo-random sequences are usually used. There are several requirements for pseudo-random sequences [2]:
(1) They should have good pseudo-randomness, that is, they should have randomness similar to that of random sequences.
(2) They should have good autocorrelation, cross-correlation and partial correlation characteristics, that is, the autocorrelation peak should be sharp, while the cross-correlation and partial correlation values ​​should be close to zero. This is for accurate detection at the receiving end to reduce errors.
(3) The number of random sequences should be sufficient to ensure that there are enough addresses provided to different users in the code division multiple access communication system.
According to the different ways of constructing the local code group generator, the error code tester can be divided into many types. This paper adopts the bit-by-bit detection type, and the code group used is the maximum length linear shift feedback register sequence, that is, the m-sequence. Its working principle is: the m-sequence generated by the local m-sequence generator is compared bit by bit with the received m-sequence. If the two m-sequences are synchronized, the comparator outputs the transmission error; if the two m-sequences are not synchronized, the comparator outputs the error caused by the loss of synchronization. Since the bit error caused by the loss of step is large (according to the characteristics of the m-sequence, its bit error rate should be 0.5), the bit error rate threshold can be used to distinguish whether the detection system is out of step. If it is out of step, let the local m-sequence generator wait for a clock cycle, then compare bit by bit in turn, and control the waiting time of the local m-sequence generator bit by bit until the two sequences are completely synchronized.
3 Hardware Design
This system uses a single-chip microcomputer as the main control chip, and the FPGA completes the bit error test work, and transmits the obtained bit error information to the single-chip microcomputer. The single-chip microcomputer calculates the bit error rate and sends it to the LCD screen for display. The sending and receiving of the m-sequence are both carried out through the RS485 interface. The single-chip microcomputer of this system uses the 51 series STC89LE58RD+, which is powered by 3.3 V, which can reduce the power consumption of the system. The FPGA uses the XC2S300E of the SPARTNANII-E series of Xilinx, which includes 300,000 logic gates and other rich resources, which can meet the needs of this system. The RS485 interface chip is ADM4857 from Analog Devices, which is a 10 Mb/s full-duplex 485 interface chip [3-4]. The hardware block diagram of the system is shown in Figure 2.

4 Software Design
The software part is the core of the system function realization, mainly including two parts: single chip microcomputer and FPGA.
(1) Single chip
microcomputer software As the main control chip of the system, the single chip microcomputer mainly completes the functions of FPGA communication control, bit error rate calculation, LCD display control, etc. After power on, the single chip microcomputer control system enters the suspended state, waiting for the start button to be pressed. After starting work, the single chip microcomputer requests the FPGA to refresh the bit error data once every 1 s, and the FPGA transmits the bit error data to the single chip microcomputer through the SPI bus. The single chip microcomputer converts the obtained bit error data into the bit error rate and sends it to the LCD display together with the obtained system transmission delay time. The flowchart of the single chip microcomputer software is shown in Figure 3. [page]

(2) FPGA logic design [5-6]
Most functions of this system are implemented through FPGA, and the program is written in Verilog. Since a bit-by-bit comparison scheme is adopted, the m-sequence generation module first generates an m-sequence with a bit rate of 4.096 Mb/s and sends it to the inverter as the source. The inverter is set to artificially generate bit errors. When the button is pressed, the inverter is enabled, and the m-sequence is inverted by 1 bit and then output, which is equivalent to generating 1 bit error. The m-sequence and clock are simultaneously output to the system under test, and then returned to the bit error tester after passing through the system under test. The bit error tester synchronizes the input m-sequence and the locally generated m-sequence. After synchronization, 64-bit m-sequence data is placed in the fixed register. At the source end, the fixed register and the shift register are continuously compared until the two are consistent, then the delay counter is started, and the shift register at the receiving end is compared with the fixed register. When the two are consistent, the counter is turned off. At this time, the value in the counter is the delay of the system under test. On the other hand, after synchronization, bit error statistics are started. If the bit error rate is greater than the set threshold value within the set test cycle, it is considered out of step and synchronization is restarted. Finally, the bit error number and system delay number are sent to the microcontroller through the SPI interface to calculate the bit error rate and system delay, and the calculation results are displayed on the LCD. The SPI interface is simulated by software. The module block diagram inside the entire FPGA is shown in Figure 4.

5 System Design Simulation
The main functional modules after the design are completed are simulated to verify the correctness of their functions.
(1) Simulation of m-sequence generator
This design uses a 23-level m-sequence to ensure the characteristics of the pseudo-random sequence. Its primitive polynomial is f(x)=1+x5+x23. The simulation waveform is shown in Figure 5.

(2) SPI interface simulation
FPGA and MCU use SPI interface for communication. The peripheral device interface SPI usually has 3 to 4 signal lines. This paper adopts 3-wire mode, namely chip select line SS, clock line SCK and data line SDIO. SS is valid when it is low, and data is transmitted under the synchronization of SCK. The simulation waveform is shown in Figure 6.
(3) System simulation
After the system starts working and synchronizes correctly, the statistics of bit errors and delays begin. Whenever the MCU sends a request data signal, it sends the current bit error number and delay number. The MCU calculates and sends them to the display for display. The system simulation waveform is shown in Figure 7.

6 Debugging
Debugging is a key step in the implementation of the entire design. After debugging, all the functions of the design were finally realized. The following are some lessons learned in design and debugging for reference.
(1) Port 1 of the 51 microcontroller does not have a pull-up resistor by default, so special attention should be paid. In the early stage of debugging, the communication with the FPGA was abnormal because no pull-up resistor was added externally.
(2) The RS485 interface chip has strict requirements on the input and output impedance matching of the differential line. It is necessary to select appropriate matching resistors according to the manual requirements, otherwise the quality of the input and output differential signals will be seriously degraded, affecting the normal operation of the system. (3) Functions such as FPGA and microcontroller communication require special attention to the timing coordination problem, otherwise it may cause abnormal communication. The timing can be adjusted by selecting an appropriate trigger edge. This paper introduces the design principle and implementation process of an FPGA-based RS485 interface bit error tester. Compared with traditional bit error testers, this bit error tester has the characteristics of simple principle, unique interface, and testable system delay. In addition, due to the good scalability of FPGA, the corresponding functions can be easily added or modified without changing the hardware circuit, which increases the scalability of the system.