CPLD Design of I2C Device Interface IP Core

CPLD Design of I2C Device Interface IP Core

According to the characteristics of the microcontroller I2C serial expansion, the IP core is established using the AHDL language in the EDA software MaxplusII environment. This design is implemented using a state machine. While giving the design, the IP core establishment process is explained in detail and downloaded to the chip for hardware test verification.

Keywords:　Programmable logic device I2C serial expansion IP core

　　Due to the trend of CPLD digital design structure, IP (Intellectual Property) cores for different levels of CPLD will appear. Each IP core can be reused, which can greatly improve the design capability and efficiency. Major foreign companies have launched special IP cores, and my country also urgently needs to develop its own IP cores. This article gives a detailed design process and results based on the characteristics of I2C master mode serial expansion communication.

1 IP Core Introduction

　　IP core refers to: some commonly used but relatively complex function blocks in digital circuits, such as FIR filters, SDRAM controllers, PCI interfaces, etc., are designed into modules with modifiable parameters, so that other users can directly call these modules to avoid duplication of work. As the scale of CPLD/FPGA becomes larger and larger, and the design becomes more and more complex, the use of IP cores is a development trend. Many companies recommend the use of ready-made or tested macro function modules and IP cores to enhance the existing HDL design methods. When designing complex systems, these macro function modules and IP cores will undoubtedly greatly reduce design risks and shorten development cycles. Using these macro function modules and IP cores, more time and energy will be spent on improving and enhancing system-level products without the need to redevelop existing macro function modules and IP cores. The construction of my country's IP core library is quite urgent, and it is an important goal for the development of the integrated circuit industry.

2 Introduction to I2C serial communication characteristics

　　The I2C software and hardware protocol launched by Philips is very clever. In the single-master I2C bus system, there is only one single-chip microcomputer on the bus, and the rest are peripheral devices with I2C bus. Since there is only one single-chip microcomputer on the bus as the master node, the single-chip system always occupies the bus, there will be no competition, and the master node does not need to have its own node address. As long as each peripheral device has its own device address, the two I/O port lines SCL (clock line) and SDA (data line) can virtualize the I2C bus interface. The data transmission on the I2C bus is shown in Figure 1. Each frame of data transmitted on the bus is 1 byte. After starting the bus, it is required that the other party respond with an acknowledge bit after each byte is transmitted. When sending, the highest bit is sent first. There is a start signal at the beginning of each transmission and a stop signal at the end. After the bus transmits 1 byte, the transmission can be paused by controlling the clock line. At this time, SCL can be made low after the acknowledge signal to control the bus to pause. The same method can also be used when the master node requires the bus to pause. Figure 1 shows the situation where the CPLD sends the two data 01010011 and 01001001 to the peripheral I2C device.

3 Establishment of I2C serial expansion IP core in MaxplusII environment

　　MaxplusII is the EDA software for CPLD developed by Altera Corporation in the United States. It has many commonly used macro units, such as counters, four arithmetic operations, various logic gates, and even ROM, RAM, etc. The specific parameters in these macro units can be set by the user, which is the IP core form mentioned above. It avoids duplication of work and improves efficiency. The IP core of the lower computer will be designed below.

　　MaxplusII's AHDL (Altera Hard ware Description Language) is a modular high-level language developed by Altera and fully integrated into MaxplusII. It is particularly suitable for describing complex combinational logic, group operations, state machines and truth tables. This article uses AHDL to directly generate IP cores.

　　The ultimate goal of the design is to generate the Symbol shown in Figure 2. The purpose of controlling SDA and SCL is achieved by inputting data, and the signal is transmitted to the I2C device according to the required timing.

　　The design idea is to use the state machine to realize the timing. It mainly includes the state machines of input data latch, start, data transmission, stop, etc. Through the state machine, in each state, it is determined whether the next state SDA and SCL are high or low. In this way, every timing required by I2C is realized. Because AHDL is used, this state machine is very convenient to implement and the program is concise and clear. Due to space limitations, only the state machine for data transmission is introduced. The state diagram is shown in Figure 3.

　　In the following program, Cmd_reg2 is the temporary storage bit for sending permission; Sh_reg[] is the data latch. By shifting left, the highest bit data Sh_reg7 is the data to be sent and is stored in SDA_tmp. By comparing the program with Figure 3, we can see the detailed process of sending a data bit using the state machine. The program list is as follows:

IF Cmd_reg2 THEN --If "transmission is allowed", Sh_reg7 will be used as the current transmission bit SDA_tmp = Sh_reg7; ELSE SDA_tmp = VCC; END IF; St.clk = SysClk; St.ena = BaudGen; CASE St IS --Control the state machine for transmitting 8-bit data WHEN t0 => IF Cmd_reg2 OR Cmd_reg3 THEN SDA = SDA_tmp; --Start transmitting data SCL = GND; St = t1; ELSE St = t0; END IF; WHEN t1 => SCL = VCC; SDA = SDA_tmp; St = t1a; WHEN t1a => SCL = VCC; SDA = SDA_tmp; St = t2; WHEN t2 => Sh_reg[7..1] = Sh_reg[6..0]; --Shift data left, take high bit Sh_reg[0] = GND; Sh_reg[].ena = EXU; SCL = GND; SDA = SDA_tmp; IF Bit[] == 7 THEN --If 8 bits are transmitted, send acknowledge bit; otherwise continue St = t3; ELSE St = t0; END IF; WHEN t3 => --Send acknowledge bit SDA = GND; St = t4; WHEN t4 => SDA = GND; SCL = VCC; St = t4a; WHEN t4a => SDA = GND; SCL = VCC; St = t5; WHEN t5 => SCL = GND; St = t6; WHEN t6 => SDA = GND; FINISHED = VCC; St = t0; END CASE; Bit[] = Bit[] + 1; ――--After transmitting one bit, the number of bits transmitted increases by one

　　Figure 4 shows the simulation results. After the start signal is given, two 8-bit data are transmitted: each data is followed by an acknowledge bit. After the first data request is transmitted, a pause is made before the second data is transmitted. After the two data are transmitted, the host sends a stop request, that is, a stop signal is given. These signals fully meet the timing requirements of I2C on SDA and SCL. To make the bus transmission rate reach the improved specification, that is, 400 kb/s, because according to the above description, each transmission of 1 bit of data requires 4 clock cycles, so the given clock is 1600 kHz. In Figure 4, Execute is the execution signal, that is, when it is high, the input data DIN[7..0] is valid; EXU is the transmission enable signal, and only when it is high can the serial data be transmitted to the peripheral device; Start is the start control signal, which is used to generate the start signal; STOP is used to inform the bus that the data transmission is over and a stop signal is generated.

　　After simulation, the generated pof file is downloaded to the FPGA board EPM7128SLC84-6 using ISP (in-system programming) through the programming cable. Pull-up resistors are hung on the I/O ports SDA and SCL. Two I2C devices SAA1064 (LED display I2C serial input and output chips) are connected externally for testing. As a result, the CPLD uses the I2C IP core and works normally, and can display as required.

References  1 Altera. ALTERA DIGITAL LIBRARY 2000 2 He Limin. Advanced Tutorial on Single Chip Microcomputer. Beijing: Beijing University of Aeronautics and Astronautics Press, 2000 3 Zhao Shuguang. Principles, Development and Application of Programmable Logic Devices. Xidian University Press, 2000 4 SAA1064 Product Specification Philps.