High-resolution graphics and image compression technology based on FH8735

This paper proposes a high-resolution graphics and image compression scheme based on the FH8735 video and audio encoder, which can complete video acquisition and compression, and send the compressed video data to the host storage through the PCI bus, or output it through the Ethernet interface to achieve remote real-time monitoring.

　　1 Overall Design

　　The high-resolution graphics and image compression solution based on the FH8735 video and audio encoder consists of an acquisition circuit, a clock circuit, an FH8735 compression circuit, a network interface, and a power supply circuit. The overall block diagram of the solution is shown in Figure 1.

　　The circuits in Figure 1 are described as follows:

　　(1) Video acquisition circuit. It consists of input matching and video acquisition circuit to complete the acquisition of high-resolution video;

　　(2) Clock circuit. It is composed of a high-performance crystal oscillator, which provides a stable clock for the video acquisition circuit and FH8735;

　　(3) FH8735 compression circuit. It consists of FH8735 audio and video encoder and DDR memory, completes video compression processing, and provides PCI interface and network interface control;

　　(4) Network interface. External PHY chip provides Ethernet interface;

　　(5) Power supply circuit: Provides the required power for each functional circuit.

　　2 Main Design

　　2.1 Video Capture Circuit

　　The video acquisition circuit is based on TI's video image decoder TVP7002. As a high-performance video image decoder, TVP7002 has the following main functions and performance characteristics:

　　(1) DC accuracy: 8/10 bits;

　　(2) Analog gain range: -6～6dB;

　　(3) Input component video signal resolution: 480i/576i～1080p;

　　(4) Input graphic signal resolution: VGA～UXGA;

　　(5) Digital video output formats: YCbCr 4:2:2 and RGB/YCbCr 4:4:4;

　　(6)I2C bus interface.

　　The video capture circuit design with the video image decoder TVP7002 as the core is shown in Figure 2:

　　After VGA video input, it can be connected to TVP7002 decoder after signal matching and filtering. The working state of TVP7002 decoder is set by FH8735 video and audio encoder through I2C bus according to signal characteristics and processing requirements.

　　2.2 FH8735 video compression

　　FH8735 is a high-performance audio and video encoding chip developed by Fudan Microelectronics. Its main technical features are as follows:

　　(1) Coding standard: ITU-T rrcommendation H.264 ISO/IEC 14496-10 advanced video coding standard (MPEG4 Part 10), support H.264 Main Profile and Baseline Profile;

　　(2) Maximum supported resolution: 2048×1024;

　　(3) Support 1-channel 1080i HD/2-channel 720pi HD/8-channel D1 input;

　　(4) 8-way I2S input interface; can be configured as master mode or slave mode;

　　(5) PCI interface, 32 bit, clock frequency 33/66 MHz;

　　(6) 2 independent DDR SDRAM controllers, each with a word width of 32 bits;

　　(7) One MII/RMII interface supports two speeds of 100/10Mbps and is fully compatible with the IEEE802.3 specification;

　　(8) One-way video output interface, compliant with BT.656 video standard;

　　(9) 2 independent I2C interfaces;

　　(10) JTAG download and debug interface;

　　(11) 16 bidirectional GPIOs.

　　FH8735 supports H.264 Main profile and Baseline profile video compression formats, and can perform real-time encoding of 8-channel 480i/576i standard-definition signals, as well as real-time encoding of one 1080i and two 720p high-definition signals. In addition to high-performance video encoding capabilities, FH8735 provides a wealth of video pre-processing functions, such as deinterlace, de-noise, OSD overlay, scaling, motion detection, etc. for input video. In order to configure external video and audio receiving chips, FH8735 provides two completely independent standard I2C interfaces to deal with possible I2C address conflicts of external devices. As an encoding coprocessor, FH8735 is equipped with a flexible host interface. The host can communicate with FH8735 for control and status information through PCI or HPI interfaces, or access FH8735's external DDR SDRAM. FH8735 has two independent DDR controllers inside, and one or two external DDR SDRAMs can be configured according to the actual system's requirements for encoder performance.

　　In order to meet the needs of some applications for preview video, FH8735 has a set of standard BT.656 video output ports, which can split and merge the multiple preview videos output by the video pre-processing unit as needed, and encode them into one BT.656 format video output.

The video compression coding circuit with FH8735 as the core is shown in Figure 3.

　　The FH8735 encoding chip receives the RGB data output by TVP7002 and completes the video compression processing according to the working status set by the host. The compressed video data can be output through the Ethernet port or transferred to the host through the PCI bus for local storage.

　　2.3 Software Design

　　The FH8735 encoding chip software development manual provides nine categories of functions: system function, video input, video preview, video encoding, OSD function, video function, area shielding, audio function, and data acquisition. The general workflow of the engineering or test software is shown in Figure 4.

　　3 Testing

　　To verify the correctness, main functions and performance of the solution, a test environment is set up as shown in Figure 5.

　　Start the test software and a dialog window will pop up as shown in Figure 6:

　　You can choose according to the specific situation of video input and video output:

　　(1) Video input: Select from three options based on the resolution of the input video;

　　(2) Video Output: Select between two options based on the video output direction.

　　Test different video input and output options separately and observe indicators such as image quality and data flow.

　　4 Conclusion

　　This solution has the following features: it can realize the acquisition and compression of 1080i60 or SXGA high-resolution video; the output bit rate can be adjusted by software control; the input image gain and contrast can be adjusted; rich video processing capabilities; the circuit structure is simple and the development difficulty is low. The high-resolution graphic image compression solution designed by this solution can have the characteristics of low bit rate, high efficiency, small processing delay and reliable operation while ensuring high-quality images. It can meet the needs of video conferencing systems, security monitoring, civil aviation management and maritime affairs, etc. that require high-resolution or multi-channel video encoding.