Data丨Xunwei IMX6ULL development board-main frequency and clock configuration routine (Part 2)

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Data丨Xunwei IMX6ULL development board-main frequency and clock configuration routine (Part 2) [Copy link]

Continued from the previous article: as follows
This register uses two bits:
STEP_SEL: Select the setp_clk clock source.
PLL1_SW_CLK_SEL: Select the pll1_sw_clk clock source.
At this point, we can simply organize the idea of modifying the main frequency:
1. Set the STEP_SEL bit of CCSR and set the clock source of step_clk to 24M.
2. Set the PLL1_SW_CLK_SEL bit of CCSR and set the clock source of pll1_sw_clk to step_clk=24MHz. Through this step, we set the main frequency of I.MX6ULL to 24MHz, which comes directly from the external 24M clock crystal.
3. Set CCM_ANALOG_PLL_ARMn and set pll1_main_clk (PPL1) to 1056MHz.
4. Set the PLL1_SW_CLK_SEL bit of CCSR, and switch the clock source of pll1_sw_clk back to pll1_main_clk
. After switching back, pll1_sw_clk will be equal to 1056MHz.
5. Set ARM_PODF of CCM_CACRR to 2 division, and the core main frequency is 1056/2=528MHz. PFD clock
We also need to set other PLL and PFD clocks. PLL1 has been set in the previous section. Some of the other PPL clocks are fixed
(PPL2-528MHz, PPL3-480MHz, PPL7-480MHz), and some do not need to be set for the time being (PPL4, PPL5, PPL6 correspond to audio and video and network respectively).
The next step is to set the PFD clock. NXP has officially recommended values as shown in the following table:

The 4-way PFD frequency of PLL2 uses the register CCM_ANALOG_PFD_528n. The register structure is shown in Figure 15.1.13:

The register CCM_ANALOG_PFD_528n is divided into four groups, corresponding to PFD0~PFD3, each with 8 bits. Let's take PFD0 as an example to see how to set the frequency of PLL2_PFD0.
The register bits corresponding to PFD0 are as follows:
PFD0_FRAC: The frequency division number of PLL2_PFD0. The calculation formula of PLL2_PFD0 is 528*18/PFD0_FRAC, and the settable range is 12~35.
PFD0_STABLE: Read-only bit. This bit is used to determine whether PLL2_PFD0 is stable. This bit is inverted when the new frequency division takes effect.
PFD0_CLKGATE: PLL2_PFD0 output enable bit. 1 means turn off PLL2_PFD0 output; 0 means enable PLL2_PFD0 output.
The frequency of PLL2_PFD0 is 352MHz, so you need to set PFD0_FRAC=528*18/352=27, and PFD0_CLKGATE is 0.
The settings of PLL2_PFD1~PLL2_PFD3 are similar, and the frequency calculation formula is 528*18/PFDX_FRAC (X=1~3). Therefore, if PLL2_PFD1=594MHz, PFD1_FRAC=16; if PLL2_PFD2=400MHz, (PFD2_FRAC cannot be divided evenly, take the nearest integer value) PFD2_FRAC=24,
which is actually 396MHz; if PLL2_PFD3=297MHz, PFD3_FRAC=32.
Next, configure the frequencies of the four PFDs PLL3_PFD0~PLL3_PFD3. The register used is CCM_ANALOG_PFD_480n. The register structure is shown in Figure 15.1.14:

Registers CCM_ANALOG_PFD_480n and CCM_ANALOG_PFD_528n The structure is exactly the same, the meaning of the register bits is also the same, but the frequency calculation formula is different. The frequency calculation formula is PLL3_PFDX=480*18/PFDX_FRAC (X=0~3)
Set PLL3_PFD0=720MHz, PFD0_FRAC=12;
Set PLL3_PFD1=540MHz, PFD1_FRAC=16;
Set PLL3_PFD2=508.2MHz, PFD2_FRAC=17;
Set PLL3_PFD3=454.7MHz, PFD3_FRAC=19.
AHB, IPG and PERCLK root clocks
The setting range of iMX6ULL peripheral root clocks is shown in Figure 15.1.15:

Here are the root clock setting ranges for most peripherals. AHB_CLK_ROOT can be set up to 132MHz, and IPG_CLK_ROOT and PERCLK_CLK_ROOT can be set up to 66MHz. We set AHB_CLK_ROOT, IPG_CLK_ROOT and PERCLK_CLK_ROOT to 132MHz, 66MHz, and 66MHz respectively. The settings of AHB_CLK_ROOT and IPG_CLK_ROOT are shown in Figure 15.1.16:

The above figure is the clock diagram of AHB_CLK_ROOT and IPG_CLK_ROOT, which is divided into 4 parts:
1. Used to select the clock source of pre_periph_clk. You can choose PLL2, PLL2_PFD2, PLL2_PFD0 and PLL2_PFD2/2. The PRE_PERIPH_CLK_SEL bit of register CCM_CBCMR determines which one to choose. PLL2_PFD2 is selected by default, so the default pre_periph_clk=PLL2_PFD2=396MHz.
2. The clock source for periph_clk is selected by the OR gate formed by the ERIPH_CLK_SEL bit of the CCM_CBCDR register and PLL_bypass_en2. When the PERIPH_CLK_SEL bit of the CCM_CBCDR register is 0, periph_clk = pr_periph_clk = 396MHz.
3. Set the frequency division value of AHB_CLK_ROOT through the AHB_PODF bit of CBCDR. There are 8 frequency divisions from 1 to 8. If you want AHB_CLK_ROOT=132MHz, you should set it to 3 frequency division (default): 396/3=132MHz.
4. Set the frequency division value of IPG_CLK_ROOT through the IPG_PODF bit of CBCDR. There are 4 frequency divisions from 1 to 4. The clock source of IPG_CLK_ROOT is AHB_CLK_ROOT. If you want IPG_CLK_ROOT=66MHz, you should set it to 2 frequency division (default): 132/2=66MHz.

Finally, configure the PERCLK_CLK_ROOT clock frequency. As shown in Figure 15.1.17:

It can be seen that there are two sources of PERCLK_CLK_ROOT clock, OSC (24MHz) and IPG_CLK_ROOT, which are determined by PERCLK_CLK_SEL in register CCM_CSCMR1. If this bit is 0, the clock source of PERCLK_CLK_ROOT is IPG_CLK_ROOT=66MHz. The frequency division can be configured by setting the PERCLK_PODF bit in register CCM_CSCMR1. We need 66MHz PERCLK_CLK_ROOT, so it is configured as 1 frequency division here.
Three registers are used in the above settings.
The structure diagram of register CCM_CBCDR is shown in Figure 15.1.18:

The explanation of each bit of this register is as follows:
PERIPH_CLK2_PODF: periph2 clock frequency division, 8 frequency divisions can be set from 1 to 8.
PERIPH2_CLK_SEL: Select the master clock of peripheral2. Modifying this bit will cause a handshake with MMDC. After the modification is completed, you need to wait for the handshake to complete. The handshake completion signal is indicated by the specified bit in the register CCM_CDHIPR. Select PLL2 for 0; select periph2_clk2_clk for 1. PERIPH_CLK_SEL: Select the master clock of peripheral2. Modifying this bit will cause a handshake with MMDC. After the modification is completed, you need to wait for the handshake to complete. The handshake completion signal is indicated by the specified bit in the register CCM_CDHIPR. Select PLL2 for 0; select periph_clk2_clock for 1.

AXI_PODF: axi clock division, 8 types of divisions can be set from 1 to 8.
AHB_PODF: ahb clock division, 8 types of divisions can be set from 1 to 8. Modifying this bit will cause a handshake with the MMDC, so after the modification is completed, you need to wait for the handshake to complete. The handshake completion signal is indicated by the specified bit in the register CCM_CDHIPR.
IPG_PODF: ipg clock division, 1~4 division can be set.
AXI_ALT_CLK_SEL: axi_alt clock selection. Select PLL2_PFD2 for 0; select PLL3_PFD1 for 1.
AXI_CLK_SEL: axi clock source selection. Select periph_clk for 0; select axi_alt clock for 1.
FABRIC_MMDC_PODF: fabric/mmdc clock division setting, 1~8 division can be set.
PERIPH2_CLK2_PODF: periph2_clk2 clock division, 1~8 division can be set.
Register CCM_CBCMR structure diagram Figure 15.1.19:


The explanation of each bit of the register is as follows:
LCD IF1_PODF: lcdif1 clock division, 8 divisions can be set from 1 to 8.
PRE_PERIPH2_CLK_SEL: pre_periph2 clock source selection. 00 selects PLL2, 01 selects PLL2_PFD2, 10 selects PLL2_PFD0, and 11 selects PLL4.
PERIPH2_CLK2_SEL: periph2_clk2 clock source selection. 0 selects pll3_sw_clk, and 1 selects OSC.
PRE_PERIPH_CLK_SEL: pre_periph clock source selection. 00 selects PLL2, 01 selects PLL2_PFD2, 10 selects
PLL2_PFD0, and 11 selects PLL2_PFD2/2.
PERIPH_CLK2_SEL: peripheral_clk2 clock source selection. 00 selects pll3_sw_clk, 01 selects osc_clk, and 10 selects pll2_bypass_clk.
Next is the register CCM_CSCMR1, the structure is shown in Figure 15.1.20:

In this register, we mainly use the PERCLK_CLK_SEL and PERCLK_PODF bits, which are explained as follows:
PERCLK_CK_SEL: perclk clock source selection. 0 selects ipg clk, and 1 selects osc clk.
PERCLK_PODF: perclk clock division, which can be set to 8 divisions from 1 to 8.
It should be noted that when we modify the configuration of the following clock selectors or dividers, it will cause handshake with MMDC:
1.mmdc_podf, 2.periph_clk_sel, 3.periph2_clk_sel, 4.arm_podf, 5.ahb_podf. After the handshake signal occurs, you need to wait for the handshake to be completed. The register CCM_CDHIPR stores whether the handshake signal is completed. If the corresponding bit is 1, it means that the handshake is not completed. If it is 0, it means that the handshake is completed. It is very simple. I will not list the various bits in the register CCM_CDHIPR one by one.
When modifying arm_podf and ahb_podf, you must first turn off its clock output and turn it on after the modification is completed. Otherwise, there may be no clock output after the modification is completed.
So far, the clock system of iMX6ULL has been explained. The clock system of iMX6ULL is relatively complex. You should learn it in conjunction with the clock-related structure diagram in the "I.MX6ULL Reference Manual.pdf".

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