Design and analysis of bit synchronization extraction in digital communication system based on single chip microcomputer

In a digital communication system , the transmitter transmits each code element in a digital pulse sequence one by one in a certain time sequence. The receiver must have an accurate sampling decision moment to correctly judge the transmitted code element. Therefore, the receiver must provide a timing pulse sequence that determines the sampling decision moment. The repetition frequency of this timing pulse sequence must be consistent with the transmitted digital pulse sequence, and the received code element must be sampled and judged at the best decision moment (or the best phase moment). The generation of such a timing pulse sequence at the receiver can be called code element synchronization, or bit synchronization.

　　The methods to achieve bit synchronization are similar to carrier synchronization. There are two methods: direct method (self-synchronization method) and pilot insertion method (external synchronization method). The direct method is divided into filtering method and phase-locked method. The method introduced in this article is implemented using the phase-locked loop in the direct method.

　　1 Principle of digital lock phase synchronization extraction

　　The digital communication system receiving end bit synchronization extraction usually adopts the digital phase locked loop DPLL (Digital Phase Locked Loop) as shown in Figure 1. DPLL consists of three components:

　　(1) The digital phase detector (DPD) compares the phase of the received code element with the bit synchronization clock output by the local DCO and outputs a digital signal reflecting the phase difference.

　　(2) The digital loop filter (DLF) filters the phase error digital signal output by the DPD, removes the influence of random noise, and outputs a more accurate phase error digital signal.

　　(3) Digital Controlled Oscillator (DCO) is an oscillator composed of digital circuits. It outputs a bit-synchronous clock pulse CLK at the same rate as the received code element. Its phase can be advanced or delayed by the phase error digital signal and is finally phase-locked with the received code element.

　　DPD and DCO are essential components of a digital phase-locked loop, and DLF can be added as needed. Each of the three components consists of a variety of circuits to form different digital phase-locked loops. The most typical digital phase-locked loop is a lead-lag digital phase-locked loop, also known as a differential rectification digital phase-locked loop, which can be implemented by the single-chip microcomputer system shown in Figure 2 when the code rate is not high. In the figure, edge detection is also called zero-crossing detection. It amplifies and shapes the input data signal DK1, and then transforms its jump edge (zero crossing point before shaping) into a narrow pulse ZCD, which is sent to the external interrupt input terminal INT1 of the single-chip microcomputer. The delay circuit in edge detection can be implemented with several levels of gates. The differential rectification circuit has the same function as the edge detection circuit.

　　This digital phase-locked loop does not use DLF. The T0 timer in the MCU and its interrupt service routine realize the DCO function. When DK1 has no transition edge (no ZCD negative pulse), the MCU does not enter the INT1 interrupt service routine, and the T0 timing is the input code period Tb. When DK1 has a transition edge, it enters the INT1 interrupt service routine, first reads the current value of T0 and the expected value (Tb/2 time constant), and determines by comparison whether the DCO phase is ahead or behind the phase relationship between the DK1 data transition edge, and adjusts the DCO phase accordingly. If the DCO phase is ahead, set the T0 next cycle timing to Tb+δ to delay the DCO phase; if the DCO phase lags, set the T0 next cycle timing to Tb-δ to advance the DCO phase, and finally achieve DCO phase lock with the DK1 data phase. In short, the INT1 interrupt service routine realizes the DPD and DCO control functions, and the T0 timer and its interrupt service routine realize the DCO function. The T1 timer and its interrupt service program implement delay, i.e. phase shift, so that the phase difference between the last output bit synchronization clock CLK and DK1 (or DK2) is 0 or 180°: when the transmission system frequency band is not limited and MSK/FSK modulation and demodulation is adopted, DK1 is a square wave, and the receiving end adopts integration/sampling/judgment for detection, and the phase difference between the two should be 0, that is, CLK and DK1 data edges are aligned; when the transmission system frequency band is limited and GMSK/GFSK modulation and demodulation is adopted, DK2 (the signal of DK1 after LPF) is a bell-shaped pulse, and CLK should sample/judgment at the midpoint of DK2 code element, and the phase difference between the two is 180° or Tb/2, as shown in Figure 2(d). The T1 delay is controlled by the P1.4 input signal MSKC. The block diagram of the INT1, T0 and T1 interrupt service programs is shown in Figure 3. The main program steps after completing the initialization of the three interrupt sources and other initializations.

　　The bit synchronization extraction digital phase-locked loop is implemented by CPU2, and its P1.4 input control signal MSKC comes from CPU1 and is determined by the working mode: in FSK/MSK working mode, MSKC=1; in GMSK/GFSK working mode, MSKC=0.

　　For the received random digital signal, it can be approximately considered that the probability of 00, 01, 10, and 11 appearing in two adjacent code elements is equal, and half of them have data jumps. For a digital phase-locked loop without DLF, the phase can be adjusted once every data jump, so the phase can be adjusted once every 2Tb s on average, so the synchronization establishment time is:

　　The digital phase-locked loop with DLF has a lower phase adjustment rate than the one without DLF, so the synchronous belt is smaller than formula (5).

　　From equations (1), (2) and (5), we can see that the three performance indicators all depend on the DCO cycle adjustment step δ: the larger the δ, the larger the synchronization band, the shorter the synchronization establishment time, but the phase error increases. Therefore, δ should be selected in a compromise. Under the premise of ensuring that the phase-locked loop can be locked (synchronized), δ should be as small as possible to reduce the phase error.

　　3 This design uses a single-chip microcomputer chip to implement digital circuit related devices, which simplifies the complex logic circuit design of related devices, reduces the power consumption and cost of the system, and improves the reliability of the system. There are many ways to achieve bit synchronization. This article discusses the use of digital phase-locked loop technology to extract bit synchronization signals. In bit synchronization extraction, how to shorten the synchronization establishment time, reduce the bit error and increase the synchronization holding time are the efforts of a good bit synchronization design.