Pingtouge RISC-V low power board-RVB2601 transplanted CoreMark

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Pingtouge RISC-V low power board-RVB2601 transplanted CoreMark [Copy link]

This post was last edited by Hot Ximixiu on 2021-7-15 08:24

RVB2601 transplant CoreMark

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The main IC on the RVB2601 development board, CH2601 is a RISC-V architecture microcontroller. The data sheet describes that the main frequency can reach up to 220MHz, which is quite surprising compared to the maximum 72MHz of STM32F103 and the maximum 168MHz of STM32F407. However, it is still inferior to the maximum 480MHz of the STM32H7 series. Of course, the above data is only in the manual. If you just want to play with overclocking, of course it is OK, but it is better not to exceed the frequency given in the manual in actual products, and even use it with downclocking, otherwise your microcontroller program may easily run away or have some other problems in different environments.

To test the performance of a processor, of course, we need to run the score. Computers have Master, mobile phones have Rabbit, and microcontrollers are no exception, with CoreMark. When we need to design an embedded or microcontroller product at work, understanding the performance of a processor can help us better select the processor. It avoids us using a butcher knife to kill a chicken or a pencil sharpener to kill a cow. Of course, we should not be superstitious about running scores. After all, a product with a processor requires close cooperation between software and hardware.

The porting of CoreMark to the MCU is very simple. The following is a brief description of the porting process on RVB2601:

1. Open the ch2601_helloworld project in the SDK provided by RVB2601. This project initializes the serial port on the RVB2601 board, and the printf function is available, which is convenient for us to print information. We will transplant based on this project.

2. Add the coremark code to the src group in the ch2601_helloworld project. The files core_list_join.c, core_main.c, core_matrix.c, core_portme.c, core_state.c, and core_util.c are all downloaded from the coremark official website.

3. Provide a 10ms time axis, because the coremark code uses the CLOCKS_PER_SEC value, and this value is defined as 100 in CDK\CSKY\PACK\newlib\v7.4.3\include\time.h. If you transplant to different MCU platforms, you should pay attention to this value. For example, if you transplant to stm32, this value is defined as 1000 in keil_v5\ARM\ARMCC\include\time.h. At this time, we only need to provide a 1ms time axis.

4. Because it takes more than 10 seconds to print complete information when calculating coremark related functions, the value in ITERATIONS in core_portme.c should be modified to a reasonable value.

It's that simple. The modifications to the main.c file are as follows. Of course, an error is reported during compilation, indicating that crc16 is defined repeatedly. At this time, just comment out the crc16 function in CDK\CSKY\PACK\aos\v7.4.3\src\crc16.c.

#include <stdlib.h> 
#include <string.h> 
#include <aos/aos.h> 
#include "aos/cli.h" 
#include "main.h" 
#include "app_init.h" 
#include "oled.h" 
#include <drv/timer.h> 
#include <drv/gpio_pin.h> 
#include <drv/porting.h> 

#define TAG "app" 

static csi_gpio_pin_t pin; 
static csi_timer_t g_timer; 

volatile uint32_t w_tick = 100; 


static void timer_event_cb_reload_fun(csi_timer_t *timer_handle, void *arg) 
{ 
 w_tick ++; 
 csi_gpio_pin_toggle(&pin); 
} 


int main(void) 
{ 
 board_yoc_init(); 
 LOGD(TAG, "%s\n", aos_get_app_version()); 
  
 oled_init(); 
  
 csi_pin_set_mux(PA7, PIN_FUNC_GPIO); 
 csi_gpio_pin_init(&pin, PA7); 
 csi_gpio_pin_dir(&pin, GPIO_DIRECTION_OUTPUT); 
  
 csi_timer_init(&g_timer, 0); 
 csi_timer_attach_callback(&g_timer, timer_event_cb_reload_fun, NULL); 
 csi_timer_start(&g_timer, 10000); 
  
 printf("CPU freq %d Hz\r\n",soc_get_cpu_freq(0)); 
  
 extern void coremark_main(void); 
 coremark_main(); 
  
 while (1)
 { 
  //LOGD(TAG, "Hello world! YoC"); 
  aos_msleep(1000); 
 } 
  
 return 0; 
}

Download the transplanted code to RVB2601, and you can see the serial port debugging assistant print the following information

[ 0.020]INIT Build:May 11 2021,14:10:50

[ 0.020]app e5

CPU freq 196608000 Hz

2K performance run parameters for coremark.

CoreMark Size : 666

Total ticks : 1547

Total time (secs): 15.470000

Iterations/Sec : 517.129929

Iterations : 8000

Compiler version : GCC8.4.0

Compiler flags : level 3 (-O3)

Memory location : STACK

seedcrc : 0xe9f5

[0]crclist : 0xe714

[0]crcmatrix : 0x1fd7

[0]crcstate : 0x8e3a

[0]crcfinal : 0x5275

Correct operation validated. See README.md for run and reporting rules.

CoreMark 1.0 : 517.129929 / GCC8.4.0 level 3 (-O3) / STACK

The CPU main frequency is 196.608 MHz and the score is 517 points. I checked the official website of coremark and found that this score is lower than the 602.44 points of STM32F446RE at 180MHz. However, the performance is still very good for a single-chip microcomputer.

Here, I would like to point out that the CPU coremark score is closely related to the CPU frequency, compiler, optimization level during compilation, code running space, and whether the MCU cache is turned on. Therefore, you should still look at this score objectively when making comparisons and evaluations.

download attachment:

平头哥RISC-V低功耗板-RVB2601移植CoreMark.zip (23.99 KB, downloads: 10)