Signal Chain Basics: How to Design a 2-to-4-Wire Converter for RS-485

Multi-point data communication networks such as Profibus, Modbus, and BACnet typically require interoperability between the RS-485 two-wire, half-duplex bus system and the four-wire, full-duplex bus system. These systems can extend to hundreds of meters in length and are subject to large ground potential differences (GPD). These potential differences can exceed the common-mode voltage range of the transceiver and cause damage to the device. To eliminate GPD, galvanically isolated transceivers are used to isolate the control electronics of the bus node from the actual transceiver stage that connects to the bus. Figure 1 shows a block diagram of a hybrid network using a 2-4 wire converter.
   
To make the converter operation independent of the data rate, the converter drivers and receivers are turned on and off by the logic state of the bus. The bus is driven at every bit interval, making the converter operation independent of the signal data rate. Simple control logic ensures that drivers D1 and D2 are enabled only by a logic low activation at the output of the opposite receiver (i.e., R1 or R2). Because the bus fault protection voltage V _FS
 
> 200 mV is present at the receiver input , both receiver outputs are logic high during the bus idle period. The inverter gate inverts this logic high to a low state and enables the receiver while turning off the driver. In the half-to-full-duplex direction ( Figure 2 : from left to right), a negative bus voltage at the input of R1 activates driver D2 with a low state to the driver input. D2 responds by driving the transmit bus with a negative output voltage. When the bus voltage at the input of R1 becomes positive, D2 is immediately disabled. However, its output is high because the fault protection bias resistor R _FS forms the bus voltage V _FS . (During the entire input period, the output of R2 remains high, ensuring that R1 remains valid and D1 remains invalid)
 

 
 
In the full-to-half-duplex direction (Figure 3: right to left), a negative bus voltage at the input of R2 activates driver D1 and forces a low state to the driver input. D1 responds by driving the two-wire bus with a negative output voltage. When the bus voltage at the input of R2 becomes positive, D1 is deactivated after a delay time. During this delay time, D1 drives the bus with a negative voltage before presenting a high impedance to prevent switching transients at the output of R1.
 
We recommend that the minimum delay time produced by the R _D ?CD _time constant be 1.3 times the maximum propagation delay of the driver to compensate for tolerances in component values, inverter thresholds, and supply voltages. For a given capacitance, the required R _{D value can be determined using} Equation 1 :  
Where _tPLH-max is the maximum low-to-high propagation delay of driver D2 _{, VIT+min} is the minimum positive input threshold of the Schmitt trigger inverter, and VCC _-max is the maximum supply voltage. After D1 fails, its output remains high due to the bus voltage _VFS formed by
 
the fault protection bias resistor RFS _. When the bus voltage at the input of R2 returns to negative, D1 is immediately activated due to the rapid discharge of _CD through the discharge diode DD _{. The timing diagram in} Figure 3 shows that a remote receiver on a half-duplex bus, represented here by R , converts a negative bus voltage into a low bit. A high bit consists of a low main driver positive bus voltage and the remaining fault protection voltage _VFS   .  
The final converter design shown in Figure 4 uses two full-duplex transceivers: one configured as a half-duplex transceiver; the other in full-duplex mode. The converter has a data rate of up to 200 kbps and is powered by a single 3.3 V supply. Table 1 shows the bill of materials (BOM) for this circuit.
Table 1. Two-to-four-wire converter BOM

   
The transceiver stages of both converter ports require the isolated supplies V _ISO-1 and V _ISO-2 to be derived from a central 3.3V supply. A schematic is shown in Figure 5. To avoid output peak requirements during no-load conditions, each rectified output includes a minimum load resistor of 2 kΩ.
   
Summary A
two-to-four-wire converter can be used to connect a single half-duplex transceiver or a complete half-duplex bus to a full-duplex bus. When connecting a two-to-four-wire converter to a full-duplex bus, it is important to note that the master node's microcontroller will change its transmission format from full-duplex to half-duplex when communicating with the converter node.