Single-Supply, Low-Power Programmable Window Detector (CN0182)

Circuit Function and Advantages

The circuit shown in Figure 1 is a single-supply, low power, window detector with programmable upper and lower limits. This type of circuit can be used to generate an alarm when a signal exceeds preset limits and is popular in sensing and monitoring applications. The AD5668-1 octal, low power, 16-bit, buffered voltage output DAC is used to set the window limits. The AD5668-1 contains an on-chip 1.25 V, 5 ppm/°C reference with a full-scale output range of 0 V to 2.5 V. The internal reference is enabled by a software write. An SPI interface is used to communicate with the AD5668-1.

The comparator used is the ADCMP370 general-purpose, low-power comparator (20 W at 5 V, typical) with 9 mV input offset voltage (maximum) and open-drain output.

Figure 1. Low-Power, Single-Supply Window Detector (Simplified Schematic; All Connections and Decoupling Not Shown)

Circuit Description

The circuit shown in Figure 1 is an upper and lower programmable window detector. The upper and lower limits are loaded into each DAC register individually. The main application of this circuit is to test whether an external signal falls within the programmed limits.

The AD5668-1 is an octal DAC with outputs on Channel A and Channel B setting the upper and lower limits, respectively.

For test purposes, DAC C provides the signal input. When the signal enters the region set by DACA and DAC B, the voltage on TP1 becomes a logic 1, LED1 turns off, and LED2 turns on. When the signal exceeds the window set by the upper and lower limits, LED1 turns on and LED2 turns off.

If you connect a pull-up resistor to the output of the ADCMP370, the output will be 5 V if the non-inverting input is greater than the inverting input; otherwise the output will be 0 V.

The ADCMP370 has open-drain outputs that allow the outputs of comparator C1 and comparator C2 to be wired-ANDed together. Table 1 shows the truth table for this circuit. In this example, VOUTA is the upper limit, VOUTB is the lower limit, and VOUTA > VOUTB.

The circuit operation is shown in Figure 2. DAC C generates a 0 V to 2.5 V triangle waveform that drives the VINC (TP2/TESTC) input to the comparator. The threshold levels are set by DAC A (VOUTA = 2 V) and DAC B (VOUTB = 1 V). When the VINC voltage is between the two thresholds, the voltage at TP1 becomes a logic 1.

Table 1. Truth table of the circuit

Figure 2. Output of the window comparator with VOUTA = 2V, VOUTB = 1V, and VINC = 0V to 2.5V ramp.

Common changes

The AD5668-2 and AD5668-3 contain an internal 2.5V, 5 ppm/°C reference, which allows a full-scale output range of 0V to 5V.

The AD5668-1 and AD5668-2 contain a power-on reset circuit that powers up to 0 V until a valid write occurs. The AD5668-3 powers up to midscale.

Circuit Evaluation and Testing

Equipment requirements (equivalent equipment may be substituted)

EVAL-SDP-CB1Z System Demonstration Platform

CN-0182 Circuit Evaluation Board (EVAL-CN0182-SDZ)

CN-0182 Evaluation Software

Tektronix TDS2024, 4-channel oscilloscope

HP-E3630A 0V to 6V, 2.55A ±20V, 0.5A Triple Output DC Power Supply

PC (Windows® 32-bit or 64-bit)

Get Started

Load the evaluation software by placing the CN-0182 Evaluation Software CD into the CD drive of the PC. Open My Computer, locate the drive that contains the evaluation software CD, and open the Readme file.

Follow the instructions in the Readme file to install and use the evaluation software.

Functional Block Diagram

Figure 3 shows a functional block diagram of the test setup.

set up

Connect the 120-pin connector on the EVAL-SDP-CB1Z circuit board to the CON A or CON B connector on the EVAL-SDP-CB1Z evaluation (SDP) board. Use screws to securely secure the two boards using the holes provided at the ends of the 120-pin connectors. After successfully setting the dc output power supply to 5 V and 3.3 V outputs, turn off the power supply.

With power off, connect a 5 V supply to the J1-1 pin (AVDD), GND to the J1-2 and J2-2 pins (AGND and DGND), and 3.3 V to the J2-1 pin (VLOGIC). Alternatively, place Link 2 in position B to power the digital circuitry from the USB port through the SDP board (default setting). VLOGIC is not required in this example.

Apply power and connect the USB cable that comes with the SDP board to a USB port on the PC. NOTE: Do not connect the USB cable to the micro-USB connector on the SDP board before applying dc power to the EVAL-CN0182-SDZ.

test

After setting up the test equipment, connect the oscilloscope probes to the test points labeled TP1, VOUTA, VOUTB, and TP2/TESTC.

The included software allows the VOUTA and VOUTB values ​​to be set, thus defining the window. If the default settings are kept, press “triangle” in the main software window to create a triangle signal on VINC, as shown in Figure 2. The duration and amplitude of this signal can be varied. This signal can be observed at the TP2/TESTC test point. With a duration of 1 second, the two LEDs flash as the VINC value enters and exceeds the limits while VOUTA and VOUTB settle to 2000 mV and 1000 mV, respectively, as described in the Circuit Description section. The AD5668-1 DAC limits the maximum values ​​of VOUTA, VOUTB, and VINC to 2.5 V.

Placing link 5 in position A allows an external signal, VINC, to be applied to the VIN pin. This signal can be observed at the TP2 test point. Additionally, the output can be observed at the TP1 test point.

When Link 1 is not inserted, the output varies according to the level of VINC relative to VOUTA.

Table 2. Jumper Settings (Bold text indicates default settings)