Sharing experience on independent design of complex module interfaces

1. Introduction

In the increasingly developed communication world, new products and new devices emerge in an endless stream. The problem that follows is that the interfaces between various products and devices are becoming more and more diverse. Although many interface standards have been defined by standardization organizations, such as USB and PCI, new interface protocols continue to emerge due to differences in performance, price, application scope, and other factors. How to design interfaces has always been a problem for electronic engineers, especially for complex interface protocols. In foreign countries, special software for interface design has been launched.

In the past year or so, we have studied the high-performance serial bus IEEE-1394 (2000A) and designed the physical layer and link layer chips based on IEEE-1394 (2000A). In the process of chip design, we studied and designed the PHY/link interface in the IEEE-1394 (2000A) chip and explored some experience in interface design. Now we take the IEEE-1394 interface as an example to share our experience with you, hoping to serve as a starting point for discussion.

2. Interface Function Structure Analysis

The main function of the interface is to enable data to flow freely between different modules or systems through the interface to achieve the purpose of data sharing. There are many reasons for applying interfaces. Usually, we use interfaces because the protocols between modules do not match. There are also various other reasons that force us to use interface technology, such as the harsh transmission environment, which requires the interface to transmit data safely according to a certain protocol. A typical example in this regard is the air interface protocol of the GSM system and CDMA. In the IEEE-1394 protocol, the interface is mainly defined to connect the physical layer and link layer application-specific integrated circuits (ASICs) of the 1394 serial bus interface of the same manufacturer or different manufacturers, and to provide support for future upgrades of the 1394 system. Domestic electronic engineers should learn from this experience in the system design process.

In a word, with the emergence of various new devices and new products, the widespread application of interfaces is self-evident. It requires us to solve the problem of data interconnection efficiently and quickly according to different situations.

In the application interface environment, the situation is always like this: the data input and output of module A adopts one interface protocol M, while the data input and output of module B adopt another interface protocol N, so data cannot be directly transferred between module A and module B, and module A and module B cannot be directly interconnected.

The usual solution is to add an interface between module A and module B. In this way, the interface receives the data sent by module A using protocol M, decomposes the data in the interface, forms data packets according to protocol N, and sends the data packets to module B. In this way, module B can receive all data packets sent by module A.

3. Independent design of complex module interfaces

Usually when we say that an interface is complex, we mainly mean that the interface connection protocol is very complex. Usually, it must process the access of complex data in many registers and multiple packaging forms at high speed. For interface designers, they must fully communicate with the designers of the interface connection modules to obtain sufficient information in order to design effective interface connection modules A and B. This will inevitably require the interface designer to communicate with the designers of modules A and B many times to jointly formulate the interface design plan. Such communication takes a lot of time and may cause disputes during the design handover, so interface documents must be formulated between design teams. Such a complex workflow makes it difficult to ensure high efficiency and high accuracy of the design.

During the design implementation, we changed the usual interface design structure. With the support of this structure, we were able to quickly design the interface we needed. After only a few discussions, the designers of each module understood how to connect the modules, allowing us to design this complex interface in a relatively short time.

We can see that the difference from the general interface function structure diagram is that a send-receive buffer is added between the interface and the module to store the data that the module needs to provide when the interface is connected to transmit data, including the values ​​of the corresponding registers and the data packets that need to be transmitted.

When designing the interface, you only need to agree with the PHY module designer to put the required information under that register address, and work together to formulate the register and send and receive data packet lists. The designer can even directly provide a register and send and receive data packet lists to both modules of the interface. In this way, the interface designer can have more room to play, thereby enabling the interface designer to carefully analyze the interface requirements and design an interface with better performance.

Next, we take the PHY/link interface between the IEEE-1394 bus physical layer and link layer chips as an example to discuss the independent design of the interface.

4. Introduction to High-Performance Serial Bus IEEE-1394

IEEE-1394A is not just a new technology that can only be used in certain fields. It has a wide market space and may even become the bus standard of the future. Although IEEE-1394A has not yet been widely adopted by PC manufacturers, its important role in the field of digital images has attracted the attention of the world. As an open technical standard for data transmission, IEEE-1394A is used in many fields. At present, the most widely used field of IEEE-1394 technology is still the field of digital images, and the supported products include digital cameras or camcorders. However, the potential market of IEEE-1394 is far more than these. Whether in computer hard disks or network interconnection, the protocol has a wide range of uses. In general, IEEE-1394A has the characteristics of low cost, small space occupation, high speed, hot plug support, and support for synchronous and asynchronous transmission.

In terms of system structure, the IEEE-1394 system is divided into application layer, management layer, transaction layer, link layer and physical layer (PHY). The physical layer and link layer are relatively stable and have high performance requirements, so they are often made into ASIC, and the rest are usually completed by related software.

The interface defined here is used to connect the physical layer and link layer application-specific integrated circuits (ASICs) of the 1394 serial bus interface of the same or different manufacturers, and provides support for future upgrades of the 1394 system. In IEEE-1394A, the PHY/link layer interface is listed in a separate chapter, which shows its importance. Based on IEEE-1394A, this article proposes a solution for this interface, and its performance has been verified to meet the indicators required by the protocol.

5. Introduction to Complex Digital Logic EDA

EDA (Electronic Design Automation) is a method of designing digital, analog, and mixed digital and analog electronic circuits on a computer platform using software development tools. It is the most dynamic and promising technology in the field of electronic design. Among them, digital logic design is relatively mature. Compared with traditional design methods, EDA tools shorten the design cycle, reduce development costs, and improve design reliability.

The complex logic design of the PHY/link interface of IEEE-1394A uses advanced EDA technology to perform top-down design. The results of the logic design are further made into ASIC after being verified by FPGA/CPLD. The development of complex logic requires two parts of tools: 1) logic simulation and synthesis tools; 2) FPGA/CPLD layout and routing tools;

FPGA/CPLD are both programmable logic devices, with many manufacturers and different models. The more typical ones are Xilinx's FPGA (field programmable gate array) device series and Altera's CPLD (complex programmable logic device) device series. Using FPGA/CPLD chips for system development has the following advantages:

Powerful functions can be realized. With the continuous improvement of VLSI technology, the number of logic gates on a single chip has reached millions of gates, and a variety of special modules are embedded. The functions that can be realized are becoming more and more powerful, and system integration can also be achieved.

Low R&D investment. FPGA/CPLD chips are reliably tested before leaving the factory. Designers only need to complete the functional design of the chip through the relevant software and hardware environment, thus saving a lot of potential costs.

The development cycle is short and the EDA design method is used. Designers do not need to have in-depth knowledge of specialized ICs. They can complete the logic design of the circuit and the production of the chip in a relatively short period of time and quickly bring the product to market.

Online programming. Based on SRAM/FLASH FPGA/CPLD, users can repeatedly program, erase, debug/upgrade, which is very convenient, and can also use the same chip to achieve different functions.

FPGA/CPLD development tools include software and programmers. Development software is generally provided by chip manufacturers, and there are also some excellent third-party software available. EDA development software includes input tools, compiler simulation tools, synthesis tools, and layout and routing, layout design and other tools. The use of Verilog high-level hardware description language makes logic design input simpler and more accurate.

The EDA tools used in the design and test are: hardware description language Verilog, simulation tool ModelSim, synthesis tool Synplify, layout and routing tool Maxplus, etc. The design and test adopts the ACEX1K series low-priced CPLD chip of ALTERA, which has more than 30,000 basic logic units and embedded storage units, which can basically meet the general logic design requirements.

6. Introduction to interface structure and function

The interfaces belong to the physical layer and link layer modules of the IEEE-1394 node system, and are submodules of the physical layer and link layer, responsible for the transmission of control signals, data packets, and status reports of the physical layer and link layer. The six signal lines Ctrl[1:0], Dn[n:0], LReq, LPS, LinkOn, and SClk are mainly used to transmit control signals and various data packets between the physical layer and the link layer.

When the link layer obtains control of the interface, the following packets may need to be transmitted: read data request packet (RdReg), write data request packet (WrReg), immediate arbitration request packet (ImmReq), fair arbitration request packet (FairReq), priority arbitration request packet (PriReq), and isochronous arbitration request packet (IsoReq).

When the physical layer obtains control of the interface, in addition to transmitting all data packets uploaded on the bus, it may also transmit status information packets and read request response packets.

In the 1394 bus system, the physical layer/link layer mainly implements timing services, data requests, data services, arbitration requests and arbitration services between the physical layer and link layer modules.

Ctrl[1:0] is the control signal of the interface. The same signal varies depending on the module to which the interface control belongs. Dn[n:0] is the data line of the interface, which is used to transmit the data packet of the interface and is also a unique feature of the interface. It supports S100, S200 and S400 and higher speeds. The bandwidth of the data bus is adapted to the bus speed: when transmitting at 100Mbps, the interface only uses D[0:1] to transmit data. For every 100Mbps increase in transmission speed, the interface will use two more data lines when transmitting data. Since the project requires the system to transmit at a maximum speed of 400Mbps, there are eight data lines in the interface. In this way, if the transmission speed is increased, only the analog part of the physical layer chip increases the processing frequency. In the digital part of the entire chip, the data clock frequency remains unchanged and is independent of the serial bus speed, making future system upgrades possible. The LReq signal line is used to transmit request signals, including read and write register requests and arbitration requests. According to the request, the physical layer responds to the transmission operation.

LPS is used to indicate whether the link layer power and function are normal.

In addition, the protocol also stipulates that the interface is equipped with a direct digital differential encoder (digital differentiators) strobe terminal to increase support for isolation between the physical layer and link layer chips. According to the idea of ​​independent design of the interface module, the main technical difficulties in the implementation of this interface are as follows:

The handshake protocol between the interface and the upper and lower layer modules needs to be carefully designed. Since the data packets transmitted by the interface are of different sizes, the connection between the interface and the upper and lower layer modules becomes complicated. This part of the protocol is not mentioned, and you must carefully design the protocol yourself. The goal is to make the connection between the upper and lower layer modules and the interface concise and efficient, and to reduce the transmission delay from the interface to the corresponding module as much as possible. In this way, the time consumed by the handshake of the physical layer and the link layer will also be reduced accordingly, resulting in higher data throughput.

The interface transmits data packets of various formats and functions. When transmitting different data packets, the actions and responses of the physical/link layer interface are different. If not handled properly, it will greatly increase the complexity and scale of the interface implementation.

The timing matching of Ctrl and Dn defined in the specification has become a major contradiction. The interface relies on Ctrl[1:0] to transmit and identify control signals to generate corresponding actions. When the physical layer transfers the control of the interface to the link layer, the protocol requires no more than two cycles. However, in the system, each layer needs a certain amount of time to send and identify control signals. The interface must reduce this time as little as possible so that the response module can recognize the control signal.

The following will briefly describe our implementation methods in the project for the above difficulties.

Handshake protocol between interfaces and physical/link modules

7. Handshake protocol between interface and physical/link module

The handshake protocol of the physical layer/link layer module and interface is not defined in IEEE-1394A, which leaves room for designers to think. The 1394 bus system itself is designed to provide a high-speed data transmission method, and the physical/link interface is in the path that all data flows must pass through, so when designing the protocol, our goal is to reduce the delay of data flow through the interface as much as possible to avoid the "bottleneck" effect of the interface.

Based on the above considerations, we considered this solution:

(Note: Since the physical layer and link layer modules are in an equal position, due to space limitations, I will only describe the physical layer module, and the link layer module is similar.)

In the above scheme, the functions of each pin are defined as follows:

Preq_En[1:0] is the physical layer packet transmission enable bit and represents the priority of the request. 2 'b00 means no request, 2 'b01 means the request has the highest priority and can terminate the current request in operation, 2 'b10 means the request has a lower priority and it will wait for the request being processed by the interface to be completed before executing.

Preq_Data[31:0] is the physical layer request data, including request type, packet length, speed and related parameters. 0~15 bits are request related data, 16~31 bits are packet length and format information, and the maximum supported case is 65536 packets of 32 bits (which can accommodate the largest packet in the protocol).

Preq_Pkt[31:0] is the physical layer data packet input port, which can input one 32-bit byte at a time.

PktUpdt_Req is the data update request bit of the data packet input port. The bytes on the physical data packet input port have been transmitted and the request is to update the data for transmission.

Link_Pkt[31:0] is the link layer data packet output port.

Link_Pkt_On is the link layer data packet arrival indication, which is used to determine whether the new data of the link layer has been transmitted.

INTF_Busy is the busy indication of the interface physical layer module, indicating that the interface is busy at this time. It is used to determine whether the data packet on the bus (the data packet received by the physical layer) can be transmitted to the link layer.

When the bus data packet is about to be transmitted to the link layer, the interface first sets INTF_Busy to prevent other bus data packets from being transmitted upward during this operation. At the same time, set Preq_En to set the request enable and priority. Then, when the interface physical layer module is ready, set PktUp-dt_Req. After the physical layer module detects that the signal is set, it immediately puts the data on Preq_Data. After the interface physical layer module completes the transmission, it sets PktUpdt_Req again to get the next byte of the data packet, and the interface internal counter is incremented by one. Repeat the process until the data packet is transmitted. When the link layer has a data packet request to be transmitted to the bus, the interface physical layer module transfers the bus control right and sets INTF_Busy to prevent the data packet on the bus from being uploaded. When the interface physical layer module receives the first 32-bit byte of the data packet, it sets Link_Pkt_On and Link_Pkt at the same time. After the physical layer module detects Link_Pkt_On, it reads Link_Pkt to obtain the first 32-bit data packet, increments the counter by one, and repeats this process until the data packet is received.

In the actual application process, we adopted the method of preparing data in advance. At the same time as the last bit of each 32-bit byte started to be transmitted, a request for updating the data was issued, so that there was basically no delay in the handshake protocol during the transmission of the data packet from the physical layer module to the link layer module.

At the beginning of the design, we considered replacing the request data bit with a control data packet, reading all the data into a RAM at one time, and operating it using the RAM's read and write protocol.

It is easy to see that the improved protocol shows unparalleled advantages in processing large data packets. The price paid is the increase in the number of handshake signals. Since these signal lines are inside the module, the relatively increased cost is minimal.

8. Simplification and merging of multiple packet processing state machines

The protocol stipulates that the interface must complete the transmission of data packets of various formats and functions. The transmission methods for various data packets are also different. Similarly, the corresponding operations for each request to the interface physical layer module are also different. After examining the various request operation processes, we simplified and summarized these processes many times, and finally adopted the following state machine.

When implementing the interface physical layer module and link layer module, we adopted a structure of a master state machine and a slave state machine.

The structure of the master state machine and the slave state machine is adopted, which not only greatly simplifies the state machine, but also makes the structure clear. Secondly, the arbitration request packets with similar operations are grouped into one category, and the slave control state machine is written according to the request type. In the implementation process, under the premise of the master-slave state machine, we began to use another method to write the slave control state machine based on the state of the Ctrl control line. Compared with the comprehensive results, the current improved state machine saves more than 50% of resources. From this point of view, it can be seen that the same function, different designs will produce completely different effects.

9. Ctrl and Dn timing matching

The IEEE-1394A protocol requires support for digital differential encoders, so the interface introduces differential encoding delay. At this time, if the delay from the generation of the digital signal to the corresponding signal line of the interface exceeds half of the SClk clock cycle, it can be inferred from the IEEE1394-2000A protocol that the corresponding receiving module cannot accurately receive the valid signal. Therefore, the design of the digital differential encoder has become one of the "bottlenecks" of the entire design.

10. Conclusion

Designing the interfaces between modules in complex protocols independently is a good way to speed up and simplify the design process, improve the reusability and maintainability of the design, and is worthy of attention and promotion. At present, foreign products generally use phase-locked loop (PLL) technology to multiply the external clock to eight times the frequency of SClk as the operating frequency of the system, while only part of the circuit in this interface design uses two times the frequency of SClk, which greatly reduces the requirements for components and the power consumption of the system.

The PHY/link interface plays a very important role in the IEEE-1394 protocol and has a great impact on the improvement of chip processing speed. This paper analyzes the interface and proposes a solution to solve the difficulties in the interface design. The above solution has been proven to be feasible through simulation testing after FPGA wiring.