Design of Digital Oscilloscope Based on FPGA

With the development of information technology, the requirements for signal measurement technology are getting higher and higher, and the use of oscilloscopes is becoming more and more widespread. Analog oscilloscopes need to be calibrated before use, which is troublesome to use; and digital oscilloscopes, due to the influence of the core control chip, have strict restrictions on the frequency of input signals. The core chip of the FPGA-based digital oscilloscope can reach 500,000 gates, and with high-speed peripheral circuits, it can measure signals with a frequency of 1 MHz, effectively overcoming the shortcomings of previous oscilloscopes.

1 System design

The designed digital oscilloscope system mainly uses the development environment of the Xilinx system, and establishes multiple modules such as AD sampling control module, keyboard control module, VGA display module, etc. in this environment, which greatly reduces the construction of hardware circuits and thus improves the stability and reliability of the system. The system block diagram is shown in Figure 1.

In addition, the design uses XPS to embed the 32-bit MicroBlaze microprocessor into the FPGA, realizing the embedding of programmable chips and system design on programmable chips. MieroBlaze accesses the on-chip storage module BlockRAM through the LBM bus, and then connects to peripherals through the OPB bus for interface connection and driving.

The VGA display part uses a double buffer mechanism to work. RAM is established inside the FPGA, and the cached data in the RAM is mapped to the VGA display according to a certain timing.

2 Hardware Design

2.1 Signal conditioning circuit module

The signal conditioning circuit module processes the input analog signal. Since the input voltage amplitude is between -2.5 and +2.5 V, and the AD module of the next stage uses a 12-bit high-speed A/D conversion chip ADS804, which can only perform analog/digital conversion on voltages of 0 to 2 V, the input voltage needs to be raised to 0 to 5 V first, and then the operational amplifier is used to scale it down to meet the analog-to-digital conversion requirement of 0 to 2 V.

2.2 A/D conversion circuit

The A/D conversion module adopts a parallel data processing method to store sampled data, which can simplify the hardware circuit to the greatest extent and improve the stability of the system. The sampling of the AD part uses real-time sampling technology. It can capture a single signal. The sampling rate is 10 MHz, that is, at the highest frequency of 1 MHz, real-time sampling can sample 10 points per cycle to ensure that a complete signal waveform is obtained.

2.3 Trigger Circuit Module

The trigger circuit module is an external trigger, which can realize arbitrary level triggering of analog signals. The module uses a voltage comparator to realize single triggering.

2.4 Storage Module

The storage module consists of two parts: internal storage and external storage. The external storage is built using an external circuit, and the internal storage is explained in the software part.

The external non-volatile memory module uses the E2PROM chip 24C128 with a storage capacity of 16 KB. This chip is used as the storage medium for manual storage, thereby achieving the design purpose of not losing data when power is off.

2.5 VGA display module

The VGA display module is a double buffer mechanism built into the FPGA, controlled by the embedded MicroBlaze soft core, and can switch between multiple pages. In addition, each interface can display Chinese information, color channels and measured input waveforms, and can control the display color of the display content.

2.6 Keyboard Module

4×4 matrix keyboard module realizes human-computer interaction.

Through the keyboard, you can select the oscilloscope's digital channel, analog channel, mixed channel, storage, playback, waveform left shift, waveform right shift and other functions.

3 FPGA-based software design

The hardware of FPGA mainly includes five parts: trigger circuit module, digital signal generation module, storage module, keyboard module, VGA display module, etc. The software flow chart is shown in Figure 2.

3.1 Trigger Circuit Program

After AD sampling is started, the data coming from AD is compared with the trigger word. When the set conditions are met, a trigger signal is generated and sent to the RAM controller. After selecting the trigger signal sent by the external trigger circuit and the trigger of the two internal digital signals, the RAM controller writes the sampled data into the RAM after being triggered. When the RAM is writing data, the trigger signal is suppressed; when the RAM reaches the pre-trigger depth, the trigger signal is released and waits for the next trigger to arrive.

3.2 Digital signal generation program

Using the principle of DDS, a signal generator is generated inside the FPGA. It mainly includes three parts: frequency control register, high-speed phase accumulator and comparator. The specific method is: use a data representing the average value of the signal to compare with the data obtained by AD sampling to obtain the A-channel signal with the same frequency and phase, and then trigger the counter through the A signal. After reasonably setting the counting pulse, the B-channel signal with a 45° delay and a duty cycle of 25% is obtained. Finally, the digital sine wave amplitude output is calculated for the phase value.

Data representing the average value of the signal is provided by the MicroBlaze measuring the signal.

3.3 Stored Programs

The storage module is divided into RAM storage and FLASH storage. RAM storage uses a dual-port RAM with separate writing and reading. When the waveform data meets the trigger condition, it is sent to RAM and 1,024 points are stored, of which the first 560 groups are sent to VGA display.

FLASH storage achieves the purpose of storage without loss of power. In the 20th century, a FLASH memory model AM29LV160DB was used on the development board. When the storage key was pressed, FLASH wrote the data in RAM to FLASH. According to the read-write timing diagram in the data, the state machine was used to implement this process. When the echo key was pressed, the data in FLASH was read back to the image display RAM and then displayed.

3.4 Keyboard Program

The keyboard adopts a 4×4 matrix keyboard and uses FPGA for scanning control to achieve human-computer interaction.

The keyboard subroutine mainly includes the correspondence between digital channel, analog channel, mixed channel, storage, playback, waveform left shift, waveform right shift, vertical sensitivity gear setting, scanning speed gear setting and other functions and keys.

3.4.1 Display Resolution Analysis

The vertical direction is divided into 10 div, and 3 levels of vertical sensitivity are set: 1 000 mV/div, 100 mV/div and 10 V/div, that is, each div can represent 1 000 mV, 100 mV and 10 mV.

The input signal voltage of the analog signal input terminal of the A/D conversion module is 0~2 V. When the oscilloscope is displayed at full scale, the amplitude of the measured signal will be: V11=1 V/div×10 div=10 V, V12=0.1 V/div×10 div=1 V, V13=10 mv/div×10 div=100 mV. The full-scale input value of the A/D converter is Vmax=2 V, and the gain of the programmable amplifier circuit is AN=Vmax/VIn, where N=1, 2, 3, corresponding to the gains of 3 different vertical sensitivities: A1=2/10=0.2; A2=2/1=2; A3=2/0.1=20.

The full-scale input value of the A/D converter is Vmax = 5 V < 10 V. The AD sampled value and the digital signal value are counted and stored according to the current gear position, that is, one is saved for every 10 points at 1 μs/div, one is saved for every 10,000 points at 1 ms/div, and one is saved for every 10,000,000 points sampled at 1 s/div.

3.4.2 Scan rate analysis

The conversion rate of A/D depends on the frequency range of the measured signal or the requirement of DSO for scanning speed. The designed scanning speed includes 1 ms/div, 1μs/div, and 1 s/div. The highest sampling rate of 16 MS/s is achieved by establishing a frequency division circuit inside the FPGA. There are six levels for every 10 times frequency step, which increases the practicality of the oscilloscope. The horizontal display resolution is 64 points/div to ensure clear and stable display waveform.

3.5 VGA display part

The VGA display module uses a double buffer mechanism, and the soft-core MicroBlaze controls the VGA display by reading and writing video memory. The VGA display can display 3 colors, taking advantage of SOPC. The GRAM bit width is 32b, which greatly improves the speed of FPGA screen refresh. The vga_dn and GRAM are designed as BlackBox for the embedded MCU. The MCU only needs to send appropriate data to the corresponding address to display the desired waveform. The main displays implemented in this design are: background color, Chinese characters, oscilloscope display frame, and waveform data. Chinese information can be displayed on the display screen by taking characters. When partial data is integrated, these parts of data have different priorities. When multiple parts overlap, they are displayed according to the priority.

4 Overall Effect

Figure 3 is an interface that displays two digital channels and one analog channel at the same time. Channel 1 (CH1) is an analog channel, and channels 2 (CH2) and 3 (CH3) are digital channels. The input signal is a sine wave with a peak-to-peak value of 1.2 V. For channel 2, the input signal voltage is set to be high when it is greater than 0, otherwise it is a low level, so channel 2 is a rectangular wave with a duty cycle of 50%. For channel 3, the input signal is set to be high when it is greater than 3.3 V, otherwise it is a low level, so in this figure, channel 3 is a rectangular wave with a duty cycle of about 25%. It can be seen from the figure that the observed value is consistent with the calculated value.

5 Conclusion

A multi-channel digital storage oscilloscope with VGA display based on FPGA is designed and implemented. The high speed of FPGA is more suitable for high-speed data acquisition and processing than other control chips. In addition, the internal storage module of FPGA has an unmatched advantage in completing the quantitative storage speed of input signals compared with external RAM. Through testing, the design system has met various design requirements relatively well.