Analog/digital converter using low voltage differential signaling data bus

One way to overcome these problems is to use a low voltage differential signaling (LVDS) data bus. Figure 1 is a block diagram of one such analog/digital converter with an LVDS output signal driving an ASIC or deserializer.

Figure 1: Block diagram

The analog/digital converter in the figure outputs a serial data stream in the LVDS signal format. The receiving end uses a dedicated integrated circuit or deserializer that supports LVDS to restore the n-bit output.

At power-up, the A/D converter and receiver enter a two-step startup process. This startup process is the process of ensuring that the different phase-locked loops in each chip can achieve synchronous operation. First, the receiver locks itself according to the pulse frequency provided by the oscillator. The phase-locked loop of the A/D converter locks itself according to CLKIN. Then, the A/D converter outputs a column of data, which is arranged in a way called a SYNC pattern. The arrangement pattern is as follows: any number of "1"s must be followed by the same number of "0"s, and the data is clocked at the data output speed. The phase-locked loop in the receiver locks according to this SYNC pattern and sends a "LOCK" signal back to the A/D converter, notifying the A/D converter that the receiver is locked and ready to receive any incoming data. The output data consists of the following three parts: a "start bit" whose value is always "1", n bits of data, and a "stop bit" whose value is always "0". Figure 2 shows the general flow of data transmission.

Figure 2: Process

Therefore, this frame consists of n+2 bits of data, and the data flow frequency is (n+2) x fsample. As long as the receiver's phase-locked loop remains locked, data can be received continuously. If the phase-locked loop slips out of the lock range, the LOCK line will be set to a low state, and the analog/digital converter will receive a request to provide synchronous operation mode again.

The output driver of the analog/digital converter can provide a constant current source to drive a 100W terminated twisted pair, stripline or microstrip line on a printed circuit. Figure 3 shows two typical termination circuits placed near the receiver.

Figure 3: Typical terminal circuit

Figure 3A shows a simple termination configuration. The line termination of the A/D converter has a resistor to help reduce any possible reflections. This resistor also acts as a load for the constant current source to generate the output signal. Figure 3B shows another simple termination configuration, using common mode resistors as needed to reduce the common mode on the cable. This method is less commonly used. By using a differential signaling format, the number of wires between the A/D converter and the deserializer can be minimized and the magnetic field generated can be kept close to the transmission line. This reduces electromagnetic interference on these lines that may affect nearby circuits.

National Semiconductor has introduced an analog/digital converter that can provide LVDS output, which facilitates streamlined system design and meets the stringent requirements of the data bus.