Methods for improving high-speed ADC clock signals

When you test the SNR of an ADC , you might connect a low-jitter clock device to the converter's clock input pin and apply a reasonably low-noise input signal. If you are not getting the SNR datasheet performance from your converter, then there are some noise error sources. If you are confident that you have a low-noise input signal and a good layout, then a combination of your input signal frequency and the jitter from your clock device may be the problem. You will find that a "low-jitter" clock device is suitable for most ADC applications. However, if the ADC's input frequency signal and the converter's SNR are high, then you may need to improve your clock circuitry.

Low jitter clock devices may have a claimed jitter specification of 1 picosecond at best, or you can generate an equally poor clock signal from an FPGA. This can cause SNR errors in high-speed ADCs. Issues include ADC quantization noise, differential nonlinearity (DNL) effects, effective converter internal input noise, and jitter. You can determine if jitter is a problem using the formula in Equation 1, which gives the ADC SNR error caused by the external clock and pure ADC jitter.

Equation 1

In this equation, fIN is the input signal frequency of the converter. In addition, tJITTER-TOTAL is the rms jitter of the clock signal and the ADC clock input circuit. Note that fIN is not the clock frequency (fCLK). 1 picosecond jitter from the external clock device to the ADC is suitable for some but not all high speed ADC applications, as shown in Figure 1.

Figure 1: The SNR produced by jitter as a function of the input signal.

Equation 1 allows you to calculate an estimate of the required clock jitter for a specific ADC. For example, for a 70dB SNR ADC with a 100MHz input signal, you can calculate tJITTER_TOTAL to be 503 picoseconds. If the input ADC aperture jitter is 150 picoseconds, a higher estimate of the external clock jitter requirement can be obtained from Equation 2.

Equation 2

In Equation 2, tJITTER-CLK is the jitter injected into the ADC clock, while tJITTER-ADC is the ADC's aperture jitter, clock amplitude, and slew rate. Continuing with our estimation, we let tJITTER-ADC be equal to only the ADC's 150 picoseconds internal jitter and ignore the effects of clock amplitude and slew rate. Using Equation 2, the high estimate of tJITTER-CLK is 480 picoseconds.

In this article, we have only scratched the surface of some of the issues behind improving high speed ADC clock signals. We need to pay more attention to clock amplitude and slew rate because they affect system jitter. We also need to know how to implement the hardware portion of a low jitter clock circuit.

In the second clock design described in this article, you need to pay close attention to several things. Clock jitter affects the SNR performance of the ADC in terms of the ADC input frequency and the actual clock jitter. Also, don't always trust the clock device manufacturer! Before you move to production, use the evaluation board provided by the ADC manufacturer to test your clock source.