Application of Logic Analyzer Test in FPGA-Based LCD Display Control

Application of Logic Analyzer Test in FPGA-Based LCD Display Control

Abstract: As a basic instrument, logic analyzer should be widely used in the teaching of basic digital circuits. This paper introduces a design scheme of LCD display control based on FPGA. By using OLA2032B logic analyzer, the control line is monitored and analyzed to ensure the accuracy of the design scheme, or to quickly locate and solve problems when problems occur in the design. The results show that logic analyzer plays a very important role in the design, debugging and analysis of digital circuits.
Keywords: LCD; logic analyzer; bus analysis; trigger

1. Introduction
Logic analyzer is recognized as the most outstanding tool in the process of digital design verification and debugging. It can check whether the digital circuit is working properly and help users find and troubleshoot faults. The main features of logic analyzer are that it can observe multiple signals at the same time; it can trigger multiple signal lines according to high and low levels, rising and falling edges, and view the results. In basic teaching laboratories, logic analyzers should be equally important as oscilloscopes, but oscilloscopes can be seen everywhere, and logic analyzers are mostly on paper. With the maturity of many simulation software, designers can observe the output signals of controlled devices on computers. In this way, in teaching laboratories, expensive, cumbersome and difficult to maintain logic analyzers are avoided. However, there is sometimes a certain gap between software simulation and hardware output, which will cause the design results to be different from what we expected, and it is difficult to find the cause. This requires us to observe the control signals output by the hardware circuit. This article focuses on the use of logic analyzers and mainly introduces a typical application of OLA2032B independent desktop logic analyzer in EDA experimental teaching-FPGA-based LCD display control design scheme. 2. Introduction to LCD display control principle 1. LCD display control principle During the experiment, the EDA GW48-PK2 teaching experiment box provided by Tsinghua University was used, and the LCD display module was mainly used. This LCD display is a HS12864-3 LCD display, which is a graphic dot matrix LCD display. It is mainly composed of a row driver and a column driver and a 128×64 full dot matrix LCD display. It contains seven instructions, and the read and write instructions share eight data channels. It can complete graphic display and can also display 8×4 (16×16 dot matrix) Chinese characters. On the experimental box, the LCD liquid crystal display can be directly controlled by FPGA, as shown in Figure 1. FPGA saves the sub-module, generates drawing instructions, and generates corresponding timing according to the instructions and sends it to the LCD. The DDRAM controller on the LCD side receives the timing control signal and displays the image on the LCD screen.

The hardware structure of the LCD module is shown in Figure 2. The LCD screen is divided into two areas, left and right. It selects the area controlled by the current signal through the chip select signals CS0 and CS1. The read and write instructions share eight data channels, and the read and write work of the LCD display is completed through several control lines. The device has a built-in 64×64-bit display memory DDRAM. The display status of each pixel on the display screen corresponds to the data in the DDRAM one by one. The data of the DDRAM is directly used as the driving signal for the graphic display. If the data of a certain point in the DDRAM is "1", the corresponding pixel on the LCD screen will be displayed; if the data of a certain point in the DDRAM is "0", the corresponding pixel on the LCD will not be displayed. In Figure 2, IC3 is a row driver, IC1 and IC2 are column drivers, and IC1, IC2, and IC3 contain many functional devices.

Figure 2 Main hardware components of the module

By controlling the levels of the five signal pins DI, RW, E, CS1 and CS2 and sending the corresponding data to the data bus, we can perform simple operation instructions on the LCD controller, such as display switch setting, display start line setting, address pointer setting and data read/write instructions. These instructions can be divided into two categories, namely display status setting instructions and data read/write operation instructions. The operation instructions are written according to the control instruction table (Table 1).
Among them: D/I: data/instruction flag, 0 means that the signal on the data bus is an instruction, and 1 means that the signal on the data bus is data;
R/W: read/write flag, 0 means that the FPGA writes to the data bus, and 1 means that the FPGA reads the data bus.

Table 1 LCD screen control instruction table

As shown in Figure 3, in the design process, the read and write timing is very critical. To ensure the correctness of the read and write operations, a logic analyzer can be used for debugging, mainly to observe the timing relationship of the signal and the correctness of the read and write data values. The read and write timing has specific timing parameter requirements. The measurement function of the logic analyzer can be used to measure the time parameters and compare them with the read timing parameter table. The specific measurement method is detailed below.

Figure 3 Read and write operation timing

2. Design ideas
Key points of LCD display controller design: 1) LCD reading and writing is a continuous process. It is necessary to set the starting address and then write continuously. This requires a state machine to implement (LCD controller); 2) Before sending instructions to the LCD, it is necessary to determine whether the LCD state can receive instructions, that is, to read the status word first, which also requires a state machine to implement (LCD read/write interface). 3) The HS12864-3 LCD screen comes with DDRAM. Reading and writing DB[7..0] is actually exchanging data with DDRAM. 4) Since DDRAM is a parallel 8-bit data bus, in order to make data transmission as simple as possible, it is recommended to use a bidirectional 8-bit RAM in the LCD module. 5) Continuously refresh the data of each pixel of 128*64, but only generate data to refresh the bidirectional RAM. No need to worry about how to draw it on the LCD. 3. Debugging with a logic analyzer 1. Problems encountered during the design process The experimental results show that the LCD module may produce some unstable factors at intervals. The left half of the screen may not be displayed, and sometimes the screen may scroll. Sometimes scattered points may appear on the LCD display, or the image may be chaotic, as shown in Figure 4. This phenomenon is generally caused by problems with the control instructions, and the timing relationship between the control line and the data line is deviated. This phenomenon requires debugging with a logic analyzer.

Figure 4 Abnormal phenomenon of LCD display

2. Build an experimental environment Based on the above problems, we need to build an experimental environment to find possible errors in the LCD display process. The experimental equipment is mainly a logic analyzer with corresponding test accessories. If you want to store experimental data or settings, you also need to connect the logic analyzer to the PC and use the logic analyzer's supporting software to store the required data. In this way, the experimental environment of PC real-time control software + OLA logic analyzer + DUT device under test is built.

3. Connection method When the logic analyzer is connected to the circuit under test, the standard accessories of the general logic analyzer have two connection forms. One is the pin connection method, which requires a reserved pin-type test port on the experimental board. This situation usually appears on professional test boards and is relatively easy to connect; the other is the airplane head connection method. The test hook of this connection method is very small and can be hooked on the test pin of the experimental board at will. There are no special requirements for the experimental board, as shown in Figure 6. In addition, we, Beijing Ocean Xingye Technology Co., Ltd., cooperate with Pomona Company of the United States to provide many other forms of connection methods, such as micro SMD test clips, integrated circuit test clips, etc., to establish different logic analyzer test solutions according to user needs.

Figure 6 The logic analyzer is connected to the circuit under test through the airplane head

4. Use of logic analyzer
In order to solve the problems in the design more conveniently and quickly, we need to use the logic analyzer well and use its unique characteristics and rich functions to debug difficult problems. As the saying goes, sharpening the knife does not delay the chopping of wood. If you can master the test methods well, you can achieve twice the result with half the effort. Below we mainly introduce how the OLA2032B logic analyzer can play the biggest role in this design experiment.
1) Auto-Scale function After connecting the test line of the logic analyzer to the signal pin you want to observe in the circuit under test, no settings are required. Just press the Auto-Scale function key, and the signal to be tested can be displayed on the screen, which is similar to the Auto-Set function of a digital oscilloscope, bringing unprecedented convenience to the use of the logic analyzer. As shown in Figure 7, all 13 connected signals are displayed on the screen.

Figure 7 Auto-Scale function

2) Bus display
Since the number of channels of the logic analyzer is large, OLA2032B has 32 data channels. If these signals are displayed at the same time, it will appear chaotic. This is why we need to display one or several groups of signals in bus form. The number of channels in each group can be set according to the actual situation, and the signals in each group have a high-order or low-order order. For example, in this experiment, S0-S7 is the data channel shared by the read and write instructions, and the other S8-S12 are 5 control lines. For convenience, S0-S7 can be set to bus form and displayed in hexadecimal or decimal, so that the designer's instructions can be clearly understood. As shown in Figure 8, it can be seen that the data written most of the time is 0. By comparing the LCD display control instruction table, it can be seen that the blank area on the LCD screen is written.

Figure 8 Bus display

3) Channel naming
Since the logic analyzer has many channels, different channels can be distinguished by color, or each channel can be named. As shown in the figure, we define a name that matches the actual meaning for each channel, so that it is very easy to distinguish and convenient to observe the timing relationship. Channel naming can be operated on the instrument or on the computer software. The latter uses the computer keyboard and is faster.
4) Computer software
The OLA2032B logic analyzer can be connected to the computer via a USB cable. Through the supporting software, the collected signal data and settings can be read, and the instrument can be controlled on the PC. The speed of reading data and controlling the instrument is very fast, both of which can reach the speed of USB2.0. The signal waveform displayed on the computer is basically synchronized with the waveform on the computer without delay. Figures 7 and 8 are all pictures stored in the computer.
5) Trigger function
Similar to the oscilloscope, the OLA2032B logic analyzer also has rich trigger functions, including high-order multi-order triggering, or-order triggering, etc. First, you can set the state of each channel for triggering, such as rising edge, falling edge, high level, low level, etc.; secondly, you can perform pulse width triggering to capture glitches; in addition, you can perform multi-stage triggering or stage triggering, which we call both parallel and serial triggering. This triggering method can be used to analyze the packet header and packet tail of data. In our experiment, we can trigger the specified position according to the timing relationship of the signal. For example, the triggering method in Figure 8 is the falling edge of the enable terminal EN. Here, only the simplest single-channel falling edge triggering method is used.
6) Observe the timing using the measurement function
As mentioned earlier, there are strict time limits for the read and write timing of the LCD screen. If an error occurs in the display, it is likely that the read and write timing and its duration do not meet the requirements, so we need to use the cursor measurement function of the logic analyzer to find the problem. OLA2032B provides three groups of six cursors, which can measure the time difference of each cursor corresponding to the reference position and the time difference between the two cursors in each group, so that the measurement results can be compared with the LCD display parameters to find the problem. Please compare the timing relationship between Figure 8 and Figure 3.
IV. Precautions for using logic analyzers
1. Voltage of input signals
Since the voltage of digital signals is relatively low, generally within 5V, the voltage resistance of logic analyzers is relatively poor, so try not to connect high-voltage signals to logic analysis for a long time. For example, logic analyzers can sometimes be used to measure and analyze some serial buses, such as I2C, SPI and other serial buses, but logic analyzers are generally not used to analyze RS232 buses, because the voltage level of RS232 is relatively high, exceeding the voltage resistance of logic analyzers.
2. Signal threshold
The threshold is the threshold level for judging whether the signal is high or low, so for the same signal, different results may be obtained corresponding to different thresholds, so we have to choose the threshold size according to the actual situation. Some users want dual-threshold judgments, but most logic analyzers do not have this function. Generally, the logic domain value is set to the high-level threshold.
3. Storage Depth
When collecting signals, the logic analyzer will store the collected signals in the memory. According to the user's requirements, the storage depth is set according to the time required for collection and the timing resolution. The maximum storage depth of OLA2032B is 512Kbit/channel.
4. Correlation between digital signals and analog signals
The signals observed by the logic analyzer are called "pseudo signals". They are only divided into high and low levels. That is to say, only the horizontal axis of the signal observed by the logic analyzer is meaningful, which reflects the time relationship of the signal, while the vertical axis is meaningless, and it does not represent the amplitude. If there is a problem with the signal, especially crosstalk, burrs and other phenomena, if we want to know its source and cause, we need to cooperate with other instruments, such as oscilloscopes, spectrum analyzers, etc.

Summary
This article introduces the application of logic analyzer in EDA teaching, and uses the OLA2032B logic analyzer to debug the FPGA-based LCD display control design. In the process of testing, we can find that the logic analyzer plays a very important role in basic teaching and is more suitable for debugging digital circuits than oscilloscopes. Practice has proved that the logic analyzer can shorten our design time and solve problems that other instruments or software cannot solve. It is also the only solution for multi-channel timing analysis, and it can simultaneously see the multi-channel signals actually output by the hardware circuit. The OLA2032B logic analyzer launched by Beijing Ocean Xingye Technology Co., Ltd. hopes to solve the current situation of logic analyzers being on the sidelines in basic teaching. The high cost-effectiveness truly makes the logic analyzer affordable for digital circuit teaching. Here, I would like to thank the teachers at Tsinghua University for giving us such a good platform, which makes us more confident in our products.

References

[1] Xu Zhongxin. LCD display controller design. Tsinghua University EDA experiment tutorial.
[2] Kang Shiyin. Random sequence generator and LCD controller based on FPGA. Tsinghua University.
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[4] Wang Le. Use of logic analyzer. Beijing Ocean Technology Co., Ltd. website. 07.05.08.
[5] Zhou Jiaming. Comparison between logic analyzer and oscilloscope. Beijing Ocean Technology Co., Ltd. website. 07.02.15