Research and Application of Verilog HDL Blocking Attributes

In Verilog HDL, there are two types of procedural assignments, namely blocking assignments and non-blocking assignments. When a blocking assignment is executed, the RHS (right hand statement) evaluation and the LHS (left hand statement) value update are executed at once, and the calculation is completed and updated immediately. During execution, the execution of other statements in the same block is blocked. The blocking operator is " = ". Its execution is very similar to traditional programming languages. Non-blocking assignments RHS evaluation and LHS value update are executed in two steps. RHS evaluation is performed at the beginning of a unit simulation cycle, and LHS value is updated at the end of the same unit simulation cycle, without blocking the execution of other statements in the same block. The non-blocking operator is " <= ", and its execution is more like a parallel circuit, making the description of the circuit more natural. Blocking assignments and non-blocking assignments are the difficulties of Verilog HDL programming. They have both similarities and differences. In-depth analysis of their similarities and differences is of great significance to the development of hardware programs.

1 Verilog event handling mechanism

The Stratified Event Queue is a conceptual model for event management, not hardware logic. The specific implementation of events in the model is related to the algorithm strategy of the EDA software manufacturer. In IEEE-2001, Verilog divides events into five different parts, as shown in Figure 1 in chronological order.

Any triggered event can be added to any of the five event columns, but can only be removed from the active event column. That is, the events in the five event columns above will eventually be activated and placed in the active event column. The stacked event column is a hierarchical model, and the execution order of the stacked event column is arranged by priority. Any EDA software can only execute active events. Other event columns activate the events in this column in turn according to the priority level for execution.

1.1 Active Event Column

As can be seen from Figure 1, most events are put into the active event column. The active event column includes non-blocking assignment RHS evaluation. However, the update of non-blocking assignment is not in the active event column, it is listed as an independent non-blocking update event column. The active event column is the execution source of the simulation. From the beginning of the execution of the active event column to the completion of the execution of the active event column is called a simulation cycle. Events in the active event column can trigger other events such as active or inactive. When all events in the active event column are executed, the EDA software will trigger the remaining event columns in order of priority for simulation execution. However, the execution order of events in the current active event column is uncertain.

1.2 Inactive Event Column

The event list that occurs in the current simulation time and is executed after the active event list is executed, that is, the inactive event list has the second highest execution priority after the active event list. For example, the callback process with PLI routines (tf_synchronize(), vpi_register_cb(cb_readwrite)). Events in the inactive event list can also trigger other events. If an active event with a higher priority is triggered, the remaining events in the inactive event list are executed later.

1.3 Non-blocking assignment update event list

Each non-blocking assignment RHS evaluation in the active event column triggers a corresponding non-blocking assignment update event. These events are placed in the non-blocking assignment update event column and have a lower execution priority than the active and inactive event columns. Non-blocking assignment update events can also trigger other events. If there are multiple successive assignments to the same variable in the non-blocking assignment update event column, only the last one is valid and the remaining values ​​will be overwritten.

1.4 Monitoring Event List

The monitoring event column is placed after the non-blocking assignment update event column. It can be seen that the values ​​monitored by the monitoring command in the monitoring event column are all values ​​after the assignment, and the active event column $display system command can view the values ​​before the non-blocking update.

1.5 Future Event Column

When executing an event, if the event contains a delay, in order not to hinder the continued execution of the simulation, the event will be suspended and placed in the future event column. Future events include future inactive events and future non-blocking assignment update events.

Understanding blocking and non-blocking assignments requires a deep understanding of the stacked event list, which reflects the Verilog event processing mechanism.

2 Application and Analysis

Usually, non-blocking assignment generates storage elements such as registers, and the corresponding physical devices are elements with storage functions, such as registers and triggers. Blocking assignment corresponds to the wire type, which usually corresponds to the physical connection. This is the most obvious difference between the two assignment methods, and it is also an important reason why sequential logic uses non-blocking and combinational logic uses blocking. But this is not absolute. In fact, blocking assignment corresponds to the wire type and can also correspond to the register type; blocking assignment can also generate storage elements, so it cannot be understood one-sidedly. In combinational logic, latches may cause test problems and bring hidden dangers. It means that when modeling, we must first consider the problem from the hardware point of view, and form the circuit structure in our mind first. Due to the different assignment methods, the comprehensive results are very different, and improper use may lead to modeling failure. Blocking assignment also has important applications in sequential logic. In combinational logic that needs to be updated in real time, only blocking assignment can meet the requirements.

The function of the following sample code is to count the number of 1s and 0s in the transmitted data.

reg [5:0] count0, count1;

always @(posedge clk,negedge Rst_n)

begin

if(!Rst_n)

...

else

begin

count0 = 0; //Statement 1

count1 = 0; //Statement 2

for(i = 0;i <= 11;i = i+1)

begin

if(data[i] == 1)

count1 = count1 + 1; //Statement 3

else if(data[i] == 0)

count0 = count0 - 1; //Statement 4

else

count0 = count0 + 0; //Prevent latch generation

end

end

end

In this code, the values ​​of count0 and count1 must be cleared before each count, and count0 and count1 must be updated in real time. Obviously, only blocking assignment can meet the requirements. Non-blocking assignment is completed in two steps. All update events are executed simultaneously at the end of the unit simulation cycle. Only the last value is valid, so non-blocking assignment cannot complete the counting task. Blocking assignment can do a good job because blocking assignment evaluation and update are completed at one time.

In terms of events, the above-mentioned real-time update problem is often encountered in sequential logic, and non-blocking assignment is often impossible to implement. However, blocking assignment can solve the problem well.

Just as blocking assignment has important applications in sequential logic, non-blocking assignment also has irreplaceable applications in combinatorial logic. Using non-blocking assignment in combinatorial logic can transform combinatorial logic into a pipeline. The pure combinatorial logic code shown below can be executed to generate pure combinatorial logic. The synthesis result is shown in Figure 2.

input a,b,c,clk,sel;

output out;

reg out,temp;

always @(posedge clk)

begin

temp = a & b; //Statement 1

if(sel)

out = temp | c; //Statement 2

else

out = c; //Statement 3

end

If the blocking assignments ("=") in statements 1, 2, and 3 in the above code are changed to non-blocking assignments ("<="), the comprehensive result is shown in Figure 3.

The pipeline design method can be widely used in high-performance combinational logic that requires frequent large-scale calculations.

In combinational logic, if there are many non-blocking assignments in the begin and end blocks at the same time, their assignment order is concurrent. In fact, they are all assigned the value sent to the register by the previous clock. This is completely consistent with the assignment of many values ​​under the same enable control signal triggered by the same clock edge. In addition, because the data is stored in the register, it is stable when the clock edge arrives, so the stored value is reliable. This method can avoid the race hazard caused by combinational logic [2].

In related applications, non-blocking assignment can better solve the zero-time contention hazard problem. Because non-blocking assignment is completed in two steps, the non-blocking assignment update event is executed after all active and inactive events are executed, which can ensure that all sensitive variable values ​​are triggered at zero time [3].

Mixing blocking assignments and non-blocking assignments in the same always block has both advantages and disadvantages. The result of mixed use may be twice the result with half the effort, or it may be half the effort. Only by understanding its processing mechanism and deeply understanding the similarities and differences of the underlying implementation of blocking and non-blocking assignments can you use them flexibly.

This article discusses the differences, connections and application examples of blocking and non-blocking assignments in detail through the Verilog event processing mechanism. As can be seen from this article, blocking and non-blocking assignments are flexible and their underlying implementations are also very different. Therefore, when designing digital circuits, based on the expected functions and starting from the hardware implementation, the differences should be considered and carefully selected to effectively avoid errors and shorten the development cycle.