Introduction and application of ModelSim and QuestaSim functions

Introduction and application of ModelSim and QuestaSim functions

ModelSim is the most outstanding language simulator in the industry. It provides the most friendly debugging environment and is the first choice for RTL-level and gate-level circuit simulation for FPGA and ASIC design. It supports PC, UNIX, and LINUX platforms, and is a simulator with a single kernel that supports mixed simulation of VHDL and Verilog. It uses direct optimization compilation technology, Tcl/Tk technology, and single kernel simulation. The compilation and simulation speed is the fastest in the industry. The compiled code is platform-independent, which is convenient for protecting IP cores. It has a personalized graphical interface and user interface, providing users with a powerful means to speed up debugging. It fully supports the IEEE standards of VHDL and Verilog languages, as well as the IEEE VITAL 1076.4-95 standard, supports C language function calls, C models, and SmartModel logic models and hardware models based on SWIFT.

ModelSim supports RTL simulation, gate-level simulation, and timing simulation: Main features :

* Direct compilation structure is adopted, and the compilation and simulation speed is the fastest;
* Single kernel seamlessly performs VHDL and Verilog mixed simulation;
* Independent of machine and version, convenient for data migration and library maintenance;
* Machine-independent compiled code is used to protect and utilize IP;
* Simple and easy-to-use and rich graphical user interface, fast and comprehensive debugging;
* Tcl/Tk user-customizable simulator;
* Fully support VHDL/Verilog international standards, fully support Verilog 2001;
* Support numerous ASIC and FPGA manufacturer libraries;
* Integrated Performance analyzer helps analyze performance bottlenecks and accelerate simulation;
* Flexible execution mode, Debug mode can perform efficient debugging, and efficiency mode greatly improves simulation speed.
* Enhanced code coverage function Code coverage, which can report
various coverage conditions such as statement, branch, condition, * expression, toggle, fsm, etc., further improving the integrity of the test;
* The same waveform window can display multiple sets of waveforms, and can perform waveform comparison (Wave Compare) in multiple modes;
* Advanced Signal Spy function, which can easily access the signals of lower-level modules in VHDL or VHDL and Verilog mixed designs, facilitating design debugging;
* Support encrypted IP;
* Integrated C debugger, support for completing test platforms and modules in C language; support 64-bit OS;

ModelSim user interface: ModelSim design flow: ModelSim coverage verification: ModelSim Dataflow window:

QuestaSim is the first standards-based single-core verification engine that integrates an HDL simulator, a constraint solver, a decision engine, functional coverage, and a common user interface.

Key Features:

*Built-in single core simulator supports SystemVerilog, Verilog, VHDL, PSL and SystemC.

* Built-in constraint interpreter supports constrained-random stimulus generation to achieve testbench-automation;

*Supports functional verification based on PSL and SystemVerilog language assertions, and supports the industry's most famous 0-in Checkware assertion library functional verification

*Integrated support for functional coverage checking and analysis

* High performance RTL and Gate-level simulation speed

*Support high-level testbench design and debugging using SystemVerilog and SystemC

* High-performance integrated mixed-language debugging environment accelerates cross-debugging and analysis of mixed verification languages ​​(SystemVerilog, SystemC, PSL, VHDL, Verilog)

* Standards-based solutions can support all processes to protect investment in verification

* Provide the most cost-effective functional verification solution Questa AFV provides true mixed language verification Questa AFV is a single-core verification solution targeting mixed language flow. It supports SystemVerilog, VHDL, PSL and SystemC at the same time, allowing designers to choose the most appropriate language. In addition, the close connection with SystemVerilog verification capabilities and its use in the generation of constrained random test platforms and functional coverage verification is also of great benefit to VHDL users. The QuestaSim user interface is similar to ModelSim, and the commands are fully compatible.

QuestaSim Coverage检查：

QuestaSim DPI Use Flow：