Design of Power Fiber Signal Analyzer Based on ARM and FPGA

0 Introduction
With the expansion and complication of power networks and the advent of regional interconnection trends, the behavior of power systems will become more and more complex. The applicability of some original assumptions and simplified models will be further challenged and tested. In this case, rich and detailed field measured data, especially data under fault or abnormal conditions. Will undoubtedly have increasingly important value. They are not only the basis for analyzing the cause of the fault and verifying the action behavior of the relay protection, but also provide valuable information for power workers to study and understand the real behavior of complex systems and discover their laws. This power signal real-time analyzer can monitor various useful information in real time, and the power system has also put forward higher requirements for it. The continuous and rapid development of computer technology also provides guarantees for the sampling rate, analysis, processing, and display capabilities of this fiber optic signal analyzer, and provides sufficient conditions for improving monitoring reliability, accuracy, flexibility, real-time performance, and information resource sharing.
At present, the formulation and content of the IEC61850 standard have exceeded the scope of the substation automation system and expanded to other industrial control fields, becoming an international standard for industrial control based on a general network communication platform. Many power equipment manufacturers at home and abroad are conducting research and application work around IEC61850, and proposed that the development direction of IEC61850 is to achieve "plug and play" and realize "one world, one technology, one standard" in industrial control communication.

1 System composition and requirements
Combined with some excellent articles similar to this design scheme about oscilloscope instruments, and take their essence as a design reference. The fiber optic signal analyzer is mainly composed of three parts, including: interface part, A/D acquisition control part and display control part, as shown in Figure 1. Each module realizes its own function and has good portability.

In order to meet the requirements of system design, the signal analyzer must also have the following functions:
(1) The photoelectric conversion module converts the optical fiber signals from different optical interfaces into electrical signals proportional to the light intensity, completes the access and forwarding of 9-1, 9-2, GOOSE format optical signals specified in IEC61850, the access and forwarding of FT3 format optical signals specified in IEC60044-7/8, and the access of special collector optical fiber signals, and the signal conversion error and measurement range meet certain accuracy requirements. Its optical signal frequency range is 125MBit/s, and the photoelectric and electro-optical conversion error accuracy is preferably about 2%.
(2) The A/D acquisition control part realizes the acquisition, storage, display, and analysis of the instantaneous value of the electrical signal that meets certain accuracy requirements and has a sufficient sampling rate. Waveform analysis is mainly carried out around waveform quality and signal characteristics, which may include the "1" state optical level value, the rise time and fall time of the optical signal, the overshoot of the optical signal, the stabilization time of the optical signal, the frequency of the optical signal, etc. Since it needs to match the speed of the optical fiber signal, its sampling bandwidth needs to be well matched with the bandwidth of the optical signal; if possible, the sampling rate should be greater than 50 times the optical signal rate, and can also be determined according to actual conditions; and in terms of A/D conversion accuracy, 10-bit A/D is preferred, and 8-bit A/D is considered when there are difficulties.
(3) The display control part mainly realizes the information decoding, information group storage, information group identification, message information display functions, etc. of the communication schemes and requirements of GOOSE, 9-1, and 9-2 formats in the IEC 61850 protocol; and the information decoding, information group identification, information group storage, and information display functions of the FT3 format (Manchester code) in accordance with the requirements of IEC60044-7/8. It realizes the functions of MMS message information decoding, information group storage, information group identification, and message information display that meet the IEC 61850 protocol. The protocol analysis unit realizes the functions of parsing, annotating, and information calculation of the above messages; it also needs to have a certain capacity of waveform storage capacity and a certain capacity of message information storage capacity. Finally, it is displayed on the LCD screen, providing a human-computer interaction interface with good visual effects and operability.
In addition, the instrument will not affect the normal operation of the system when it is connected to the measurement signal, and it has an online monitoring function. The wiring diagram of the optical fiber signal analyzer is shown in Figure 2.

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In addition to meeting the above requirements, the analyzer also has good information storage and background analysis capabilities. It can save message information in real time. The saved frame information contains all frame information, including message header, added bytes, CRC check code and other digital information, so as to facilitate subsequent analysis.

2 Hardware Design
2.1 Interface Design
The interface control part mainly completes the reception and forwarding of optical fiber signals. The main functions completed are such as receiving and amplifying optical fiber signals; amplifying and selecting the two signals that need to be collected. The key technology of this part lies in the selection of optoelectronic/electro-optical modules. The wavelength of the optical interface is all 1310 nm, multi-mode, ST interface. The HFBR-5905 multi-mode optical fiber transceiver is mainly used. Similarly, the optical fiber splitter is also 1 310 nm, multi-mode, ST interface, and the 2-to-4 signal splitter model DS25BR204 is used.
As shown in the principle block diagram of the interface board in Figure 3, the optical signal is divided into two after optoelectronic conversion. One is provided to the signal analyzer for collection, storage and analysis, and the other is directly output and provided to the measured signal or test signal generator.

2.2 Design of A/D acquisition control board
The A/D acquisition control board is the core component of the system. Considering the high frequency of optical signals, general A/D converters cannot meet the requirements of this system design. To achieve the sampling rate required by the optical signal analyzer to be greater than 25 times or even 50 times that of optical signals, a high-speed A/D acquisition optical signal is required. As one of the core components of the system, the A/D acquisition control board mainly completes the following functions: 7-level variable gain amplification of optical analog signals; 3 GHz acquisition of optical signals; real-time signal cache, with a cache depth of 50 K×8 b; non-real-time storage of signals; rising edge detection (triggering) of signals; signal extraction; ARM interface board control interface implementation, etc. The principle block diagram of the acquisition control board is shown in Figure 4. The acquisition control board is mainly divided into three parts: acquisition front end, control storage and power management.

The acquisition front end mainly completes the functions of analog signal conditioning and signal acquisition. It is composed of ADC, variable gain low noise amplifier and clock. The key chip A/D conversion chip is ADC08D1500. [page]

The control and storage part mainly includes two parts: control and storage. The control part is mainly completed by FPGA, and its main functions include: DDR data reception, clock management, pulse detection, FLA-SH interface and ARM control interface. The storage part is completed by FPGA and NANDFLASH. FPGA provides RAM storage and NAND FLASH provides ROM storage. The key chip FPGA is selected as XC5VLX30-1FFG676C. The FPGA contains a total of 3 million gates, built-in RAM is 1,152 Kb, 400 available pins, supports up to 200 pairs of LVDS, and has 32 dedicated multiplier resources. Since the cache depth requirement is 400 Kb, the FPGA meets the cache depth requirement. The pin consumption of FPGA and AD front end is less than 100 bits, the pin consumption of FLASH is less than 60 bits, and the connection resource consumption of ARM is less than 100 bits, so the pin resources must meet the requirements. As for the number of logic gates and multiplier consumption, they also fully meet the system requirements.
The power management is mainly to generate various voltages required in the board. According to the needs of the motherboard, the power module can convert the voltage provided by the battery into multiple voltages and provide them to the motherboard. When connected to a power adapter, it can not only charge the battery but also supply power to the motherboard at the same time. The key DC/DC chip uses TPS54331 to convert 5V DC into the required DC voltages of 1.0 V, 1.8 V, 2.5 V, etc. Its structure is shown in Figure 5.

In addition, in order to save battery power and ensure the safe operation of the equipment, the system can be automatically shut down through software control when the equipment is not used for a long time.
2.3 Design of display control part
This part completes the functions of the human-machine interface, data display, protocol analysis, etc. of the entire system. The basic idea is to control other modules to amplify, select, collect and store at high speed under the set working mode, and complete tasks such as waveform display and processing. You can also select the format type of the measured signal and the switching of the test channel as needed. The functions and connection relationship of the display board are shown in Figure 6.

2.3.1 Memory interface
This part consists of three parts, namely dual-port RAM, NORFLASH and FRAM. The data of RAM comes from the ADC acquisition board, which stores the data required by the display control board in real time; NOR FLASH stores data that needs to be backed up, such as important data information detected; FRAM is the BIOS of the entire system, providing information such as the initial working state of the system.
2.3.2 IEC61850 protocol
ARM parses, annotates, and stores messages of 9-1, 9-2 and GOOSE message signals from the interface board after photoelectric conversion and acquisition board high-speed A/D conversion.
2.3.3 Human-machine interface
This part includes functions such as human-machine interaction interface control and waveform display, and realizes the display of data from the acquisition board with an LCD screen, and completes some functions equivalent to a digital storage oscilloscope through keyboard operation. Such as waveform translation, zooming in, zooming out, and switching of test channels. It enables the operator to observe the real-time working status information of the substation more directly.

3 Conclusion
This article introduces the research and design of a fiber optic signal analyzer based on ARM and FPGA to complete the acquisition, decoding, analysis, and display of real-time signals in digital substations. It can quickly and directly grasp the working status of the substation, the operation of the equipment, and useful information such as alarms and repairs. In order to make it more convenient to operate and carry, the equipment will be considered to be miniaturized and handheld in the future, which requires the equipment to have better performance in power consumption and energy saving.