Research on ARM core exception and interrupt handling mechanism

1. ARM processor exceptions and their corresponding modes

When an exception occurs, the ARM processor always switches to ARM state (not Thumb state). The Thumb instruction set does not contain some instructions required for exception handling, so ARM instructions must still be used when an exception interrupt occurs.

Each exception causes the kernel to enter a specific mode. In addition, any ARM processor mode can be entered by modifying the cpsr. User and system modes are the only two modes that can be entered without the corresponding exception.

When an exception causes a mode change, the kernel automatically:

Save cpsr to spsr in the corresponding exception mode

Save the PC to the corresponding mode of lr

Set cpsr to the corresponding exception mode

Set pc to the entry address of the corresponding exception handler

2. Vector table

A table of addresses to which ARM jumps when an exception occurs.

3. Exception Priority

The reset exception is the highest priority exception. Once a reset exception occurs, a reset exception will always occur. Note: When an instruction that does not belong to the ARM or Thumb instruction set reaches the execution stage of the pipeline, if no other exception occurs at this time, an undefined instruction exception will be generated. The ARM processor will "ask" the coprocessor to see if it can process it as a coprocessor instruction. Since the coprocessor is after the pipeline, instruction confirmation can be performed in the execution stage of the kernel. If this instruction does not belong to any coprocessor, an undefined instruction exception will be generated.

4. Interruption

Interrupt delay refers to the interval time from when an external request signal is sent to when the first instruction of the corresponding interrupt service routine (ISR) is fetched.

5. Interrupt sources and their identification methods

S3C2440A has 60 interrupt sources. IRQ has two interrupt identification methods: vector interrupt and non-vector interrupt. FIQ only has non-vector interrupt. When the interrupt request of one of the interrupt sources in IRQ is responded, the CPU automatically loads a transfer instruction to the fixed interrupt vector of the corresponding interrupt source at 0x18. The vector address of each IRQ interrupt source is fixed, and each occupies one word unit. If each IRQ interrupt source uses non-vector interrupt, any interrupt source sends an interrupt request, which is considered to have occurred. The IRQ interrupt service program is automatically transferred to the execution. The main function of the IRQ interrupt service program is to send the corresponding interrupt source service program entry address in the interrupt vector table set by the software to the PC and transfer it for execution. In the non-vector interrupt mode, a transfer instruction is generally placed at the IRQ: B IsrIRQ. Among them, IsrIRQ is the total entry address of all IRQ interrupt service programs, and is also the interrupt source judgment and scattered transfer program in the non-vector interrupt mode.

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6. Interrupt stack design

When designing a stack, two points must be determined:

Location

Determines where the stack starts in the memory map. Most ARM-based system designs use a downward descending stack with the top of the stack located at the high end of the memory address.

Stack size

Depends on the type of handler - nested or non-nested. A nested interrupt handler requires more memory space because the stack will grow with the depth of interrupt nesting.

The first method, A, illustrates a traditional stack arrangement, where the interrupt stack is located below the code segment. The second method, B, has the interrupt stack above the user stack, at the top of the memory. The advantage of B over A is that B will not corrupt the vector table when the stack overflows, so the system has a chance to correct its error after confirming the stack overflow. A stack must be established for each processor mode, which is done every time the processor is reset. Because the system reset starts from the supervisor mode, there is no need to switch to the supervisor mode, and the establishment of the stack for other modes requires switching to the corresponding mode. Used for mode stacks - usually set up last, because there is no direct way to modify the cpsr when the processor is in user mode. Since system mode and user mode share registers, the processor can be forced into system mode to set up the user mode stack.

7. Interrupt handling method

1) Non-nested interrupt processing

The simplest interrupt handling is non-nested: only when control returns to the interrupted task or process is it allowed to respond to the interrupt again. Since a non-nested interrupt handler can only serve one interrupt handler at a time, this form of interrupt handler is not suitable for complex embedded systems that need to serve multiple interrupts of different priorities.

2) Nested interrupt processing

Interrupt nesting is achieved by re-enabling interrupts before the handler has finished servicing the current interrupt. The entry code for a nested interrupt handler is similar to that of a simple non-nested interrupt handler. The difference is that on exit, the handler tests a flag that has been updated by the ISR. This flag indicates whether further processing is required. If no further processing is required, then the interrupt service routine is complete and the handler can exit. If further processing is required, the handler may take several actions: re-enabling interrupts and/or performing a context switch. Re-enabling interrupts involves switching the IRQ mode to SVC or system mode. In IRQ mode, interrupts cannot be simply enabled because this may cause the link register r14_irq to be corrupted, especially if an interrupt occurs immediately after the BL is executed. Performing a context switch involves resetting (clearing) the IRQ stack because the handler will not perform a context switch while there is data on the IRQ stack. All registers saved on the IRQ stack must be transferred to the task stack, typically on the supervisor mode stack. Then, the remaining registers must also be saved to the task stack. There, they are transferred to a reserved storage block in the stack called a stack frame.

The instructions for restoring the site are as follows:

LDMFD R13!, (R0～R3, PC)^

Here, the "^" after the register list (which must include PC) indicates that this is a special form of instruction. While the PC is loaded from the memory, the CPSR is also restored.