s3c2440 bare metal - i2c programming - 1 - i2c protocol

1. Hardware circuit

The I2C bus is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. As shown below:

SDA (serial data line) and SCL (serial clock line) are both bidirectional I/O lines, which need to be connected to the power supply VCC through pull-up resistors. When the bus is idle, both lines are high level.

The speed of I2C bus can reach 100Kb/S in standard mode and 400Kb/S in fast mode. The SDA and SCL lines must be connected to a pull-up resistor, usually 4.7K.

2.i2c protocol rules

The transmission process is as follows:

The master sends a start signal (S)

The master sends the slave device address (slave dev addr)

Master sending direction (W/R)

Slave device responds (ack)

The master (or slave) sends data (data)

Slave device (or master) responds (ack)

…

The master sends a stop signal (P)

The following figure shows the specific i2c read and write process of s3c2440:

2.1 Start & Stop Signal

Start signal: SCL is high level, SDA is pulled low by the master

Stop signal: SCL is high level, SDA is pulled high by the master

2.2 ack signal

In the 9th clock cycle, SDA is pulled low to indicate the ack signal

2.3 DATA format

8 bits of data (7 bits of slave device address + 1 bit of direction) are transmitted using 9 clks, with MSB high bit out first. The 9th clk is the ack signal.

2.4 Data Validity

The data on the SDA line must remain stable during the SCL high period and is allowed to change only when the SCL is low.

In other words, when SCL is at a high level, it indicates valid data, SDA is at a high level to indicate "1", and low level to indicate "0"; when SCL is at a low level, it indicates invalid data, at which time SDA will switch levels to prepare for the next data representation.

2.5 One-time data transmission

2.6 Principle of bidirectional transmission on one SDA line (open-pole circuit)

condition:

1. When the master device sends, the slave device does not send (it can be controlled by SCL, for example, let the first 8 clks of the master send data to SDA, and let the 9th clk of the slave device send data to SDA)

2. When the master device sends data, the "send pin" of the slave device cannot affect the SDA data. Conversely, when the slave device sends data, the "send pin" of the master device cannot affect the SDA data. So how to do it? (The internal circuit of SDA uses a transistor, an open collector circuit)

From the above figure, it can be seen that when A and B are both low, the transistor is not conducting, and the level of SDA depends on the external circuit. Here SDA has a pull-up resistor, so it corresponds to a high level.

When the master pulls A high, the transistor is turned on, SDA is grounded, and the level is pulled low

Similarly, when the slave device pulls up B, the transistor is turned on, SDA is grounded, and the level is pulled low.

Then the level truth table is as follows:

Therefore, when implementing bidirectional transmission:

If data is transmitted from master to slave, let the master drive the transistor to pull down SDA.

If data is transmitted from slave->master, let the slave device drive the transistor and pull down SDA.

Otherwise, the transistor is not driven, SDA always outputs high level and is in idle state.

From the following example, you can see how data is transmitted (to achieve two-way transmission).

Example: The master device sends (8 bits) to the slave device

⚫ First 8 clks

◼ The slave device should not affect SDA, and the slave device should not drive the transistor

◼ The master device determines the data. When the master device wants to send 1, it does not drive the transistor. When it wants to send 0, it drives the transistor.

⚫ The 9th clk, the data is determined by the slave device

◼ The master device does not drive the transistor

◼ The slave device determines the data. If it wants to send a response signal, it drives the transistor to make SDA become 0.

From here we can also know that the ACK signal is a low level. From the above example, we can know how to achieve bidirectional transmission on one line. This is why a pull-up resistor is used on SDA.

Why does SCL also use a pull-up resistor? After the 9th clock, if one party needs more time to process the data, it can keep driving the transistor to pull SCL low.

When SCL is low, no one should use the IIC bus. Only when SCL changes from low to high, the IIC bus can be used. When it is ready, the transistor can no longer be driven. The pull-up resistor changes SCL to high, and other devices can continue to use the I2C bus.

2.6 SCL is pulled low by the slave device to indicate busy state

After the 9th clk, i2c will generate an interrupt, and SCL will be pulled low, indicating a busy state, meaning that no one is allowed to use i2c anymore. Then when the interrupt processing is completed, it is in an idle state, and SCL will be released. The master can continue to send the SCL signal to indicate that i2c communication can continue.