s3c2440 bare metal - i2c programming - 2 - i2c controller

1.I2C master and slave device relationship

For write operations, the master acts as a transmitter and the slave device acts as a receiver.

For read operations, the master acts as a receiver and the slave device acts as a transmitter.

2.I2C controller

2.1 Overall Block Diagram

Pclk = 50Mhz, after being divided by the prescaler, SCL can be obtained.

IICSTAT: Sends S (start) signal or P (stop) signal.

Data Bus can write data into the IICDS register, then automatically generate SCL, and synchronize the 8-bit data from SDA to the slave dev.

After the data is sent out, it will receive an ack response from the slave dev at the 9th SCL clock. You can determine whether there is an ACK response by querying IICSTAT.

When the slave dev responds with ACK, it can continue to send data and continue to write data to IICDS.

When the master wants to end, it sets IICSTAT to send a P signal.

2.2 Register Introduction

1.IICCON (used to configure the i2c clock)

Bit[7]: For the sending mode, there is no need to configure the ack signal, which is the response sent back by the receiver. For the receiving mode, set it to 1 to send an ack signal at the 9th CLK (pulling sda low).

Bit[6]: SCL clock source, pclk frequency division is sufficient

Bit[5]: interrupt enable, must be enabled when using i2c

Bit[4]: Interrupt status flag indicates whether the interrupt has ended. When this bit is read as 1, SCL is pulled low to indicate busy, that is, the i2c interrupt is still being processed. When the i2c interrupt is processed, this bit can be cleared to 0 to release SCL.

Bit[3:0]: i2c clock division coefficient configuration, SCL clock = IICCLK/(IICCON[3:0]+1)

2.IICSTAT (configuration mode, S, P signal, check whether there is ack)

bit[7:6]: mode selection

Bit[5]: When reading, 0 means not busy, 1 means busy

When writing, 0 means writing STOP, 1 means writing START

Bit[4]: Data output enable, 0: disable, 1: enable

Bit[3]: arbitration flag

Bit[0]: Indicates whether there is an ack in the 9th clock cycle on the i2c bus. 1 indicates an ack, and 0 indicates no ack

3.IICADD (Configure slave address)

4.IICDS: (stores data to be sent or received)

3. Read and write operation process

The following steps must be executed before any IIC Tx/Rx operations.

1. Write own slave address on IICADD register, if needed.

2. Set IICCON register.

a) Enable interrupt

b) Define SCL period

3. Set IICSTAT to enable Serial Output

Before operating tx and rx, you must first perform the following steps:

1.IICADD writes the slave device address

2. Set IICCON, set clock, enable interrupt

3. Set IICSTAT to enable transmission

Operation Mode:

The S3C2440A IIC-bus interface has four operation modes:

— Master transmitter mode

— Master receive mode

— Slave transmitter mode

— Slave receive mode

①Master/Transmitter Mode

1. Configured to master tx mode (that is, IICSTAT[7:6] is configured to 11)

2. Write the slave device address into IICDS (the first transmission address)

3. IICSTAT writes 0xF0 (enables transmission, sends S signal, enables tx/rx)

4. The data configured in IICDS (slave device address 7bit + read/write bit 1bit) is sent out (an interrupt will be generated after each data is transmitted)

5. Determine whether the 9th clk slave device has ack

1. If the slave device has ack, resume i2c transmission

1. IICDS = buf

2. Clear pending bit

3. The data is sent out and the i2c transmission continues

2. If there is no ack, stop and return an error

1. IICSTAT = 0xd0

2. Clear pending bit（IICCON[4]）

3. Delay for a while to wait for the stop condition to take effect

②Master/Receiver Mode

1. Configured to master rx mode (that is, IICSTAT[7:6] is configured to 10)

2. Write the slave device address into IICDS (the first transmission address)

3. IICSTAT writes 0xB0 (enables transmission)

4. The data configured in IICDS (slave device address 7bit + read/write bit 1bit) is sent out (an interrupt will be generated after each data is transmitted)

5. Determine whether the 9th clk slave device has ack

1. If the slave device has ack, resume i2c transmission

1. Buf = IICDS

2. Clear pending bit

3. The data is received and the i2c transmission continues

2. If there is no ack, stop and return an error

1. IICSTAT = 0x90

2. Clear pending bit

3. Delay for a while

③Slave/Transmitter Mode

④Slave/Receiver Mode