Analysis of arithmetic operation instructions of MCS-51 microcontroller

MCS-51 has four powerful arithmetic operation instructions: addition, subtraction, multiplication and division.

1. Program status word PSW

MCS-51 has a program status word register PSW, which is used to save the flag of the instruction execution result for program inquiry and judgment. PSW is one of the special function registers and its format is as follows:

PSW7 - It is both the accumulator C of the Boolean processor and the carry flag CY. If the operation result has a carry output (during addition) or a borrow input (during subtraction) in the highest bit, CY is set, otherwise it is cleared to "0" CY .

AC - Auxiliary carry (half carry) flag. If there is a carry in the lower 4 bits of the operation result (during addition) or borrowing from the higher 4 bits (subtraction), set AC, otherwise clear "0" AC. AC is mainly used for binary-decimal number addition adjustment.

OV - overflow flag. If there is a carry into the highest bit of the operation result, but no carry is generated from the highest bit, or a carry is generated from the highest bit but the low bit is not carried to the highest bit, then the overflow flag is set, otherwise OV is cleared to "0". The overflow flag bit is used for complement operations. When the signed number operation result cannot be represented by an 8-bit binary number, OV will be set.

P - Parity flag bit of accumulator A. If the modulo 2 sum of the 8 bits of accumulator A is 1 (odd), then P = 1; otherwise, P = 0. Since P always represents the parity of A, it changes with the content of A, so the value of a value written to the P bit of PSW does not change.

RS1, RS0 - indicates the currently used working register area.

F0——User flag bit. It can be used as a software flag, and its function is similar to that of the internal RAM bit addressing area.

PSW1 - reserved bit, operations on it are invalid.

2. addition instruction

1. Addition instruction without carry

ADD A, #dataADD A, dataADD A, @RiADD A, Rn

The working register, the content of the internal RAM unit or the 8-bit unsigned binary number of the immediate value is added to the number in the accumulator A. The resulting sum is stored in the accumulator A. When there is a carry in the 3rd and 7th bits of the sum, AC is added respectively. , the CY flag position is 1; otherwise it is 0.

The execution of the above instructions will affect the flag bits AC, CY, OV, and P.

For unsigned numbers, the carry flag CY=1 indicates overflow; CY=0 indicates no overflow. The overflow of signed number operation depends on whether one of the 6th and 7th bits generates a carry, and the other bit does not generate a carry. The overflow flag OV is set to "1" otherwise it is cleared to "0". OV=1 means that when two positive numbers are added, the sum becomes a negative number, or when two negative numbers are added, the sum becomes a positive number.

There are four addressing modes for source operands: register, direct, indirect, and immediate.

2. Addition instruction with carry:

ADDC A, #dataADDC A, dataADDC A, @RiADDC A, Rn

These are four addition instructions with carry. Add the content of accumulator A to the content of the current CY flag, plus the unsigned single-byte number, and store the sum in accumulator A. When a carry overflow occurs in the 3rd and 7th bits of the operation result, the AC, CY and OV flags are set respectively. The execution of this instruction will affect the flag bits AC, CY, OV, and P.

This instruction is often used for multi-byte addition.

3. Add 1 command:

INC AINC dataINC @RiINC RnINC DPTR

The INC instruction adds 1 to the specified content, and the result is still stored in the original A or the original unit. If the original value is 0FFH, it will become 00H after adding 1. The operation result does not affect the flag bit.

This instruction can add 1 to the contents of the accumulator A, working register RN, RI indirect address and direct addressing unit. It can be seen that MCS-51 plus 1 instructions are relatively rich.

Note: When this instruction is used to increase the output parallel I/O content by 1, it will be used as the original value of the output port and will be read from the data latch of the output port instead of the pin of the output port.

4. Binary-decimal correction instructions:

DA A

If [(A0-3)》9] or [(AC)=1), then (A0-3)(A0-3)+06H

This instruction is to correct the BCD code addition result of A. After two compressed BCD codes are added as binary numbers, they must be corrected by this command to obtain the sum of the compressed BCD codes.

The operation of this instruction is: if the low 4-digit value of accumulator A is greater than 9 or the 3rd bit generates a carry to the 4th bit, that is, the AC auxiliary carry bit is 1, then the low 4-bit content of A needs to be corrected by adding 6. To generate the correct BCD code value for the lower 4 digits. If after adding 0 for correction, a carry occurs in the lower 4 bits and the upper 4 bits are all 1, the internal addition will set the CY bit. Otherwise, it does not clear the "0" CY flag.

If the value of the high 4 bits of accumulator A is greater than 9 or the highest carry bit CY=1, then the high 4 bits need to be corrected by adding 6 to generate the correct BCD code value of the high 4 bits. Similarly, if the highest carry occurs after adding 6 for correction, CY is set. Otherwise, if "0" CY is not clear, CY is set, indicating that the sum BCD code value is greater than or equal to 100. This is useful for multibyte decimal addition. Does not affect the OV flag.

It can be seen that this instruction adds O6H, 60H or 66H to accumulator A based on the original value of accumulator A and the status of PSW.

It must be noted that this instruction cannot simply exchange the hexadecimal number in accumulator A into BCD code, nor can it be used to correct decimal subtraction.

3. subtraction instruction

MCS-51 adds a subtraction instruction with borrowing on the basis of MCS-48, which enhances the computing function of the computer.

1. Subtraction instruction with borrow:

SUBB A, #dataSUBB A, dataSUBB A, @RiSUBB A, Rn

The subtraction instruction SUBB with borrow subtracts the carry flag CY and the specified variable from accumulator A. The result is in accumulator A. If there is a borrow in the seventh bit, bit CY is set, otherwise CY is cleared to 0. If bit 3 is misplaced, the auxiliary carry flag AC is set, otherwise it is cleared to 0 AC. If one of the 7th and 6th bits needs to be borrowed, but the other bit is not borrowed, the overflow flag OV is set. The overflow bit OV is used for signed integer subtraction, which indicates (OV=1) that the result of subtracting a positive number from a negative number is a negative number; or that the result of a negative number minus a positive number is a positive number.

The source operand allows four addressing modes: register RN, direct address, indirect address Ri or immediate number.

When the value of the carry flag CY is not known before single-byte or multi-byte subtraction, CY should be cleared to "0" before the subtraction instruction.

4. Multiplication instructions

MUL AB

The multiplication instruction is newly added to MCS-51, and the operation speed only takes 4 machine cycles. It greatly increases the computing function of MCS-51 single-chip microcomputer and overcomes the shortcomings of MCS-48 series single-chip microcomputer.

This instruction multiplies two 8-bit unsigned integers in accumulator A and register B. The lower 8 bits of the 16-bit product are stored in A and the higher 8 bits are stored in B. If the product is greater than 255 (0FFH), that is When the content of B is not 0, the overflow flag OV is set, otherwise it is cleared to "0" OV. The carry flag CY is always cleared to "0".

5. Division instruction

DIV AB

The addition of division instructions to the MCS-51 series of microcontrollers requires only 4 machine cycles in operation time. It also enhances the computing capabilities of the MCS-51, making it suitable for complex control systems that require strong computing capabilities. Division instruction format:

This instruction divides the 8-bit unsigned integer in accumulator A by the 8-bit unsigned integer in register B. The integer part of the result quotient is stored in A, and the integral part is stored in register B. Clear "0" the CY and OV flags. When the divisor (content in B) is 00H, the execution result will be an indefinite value, that is, the execution result sent to A and B is an indefinite value, and the overflow flag OV is set. In any case, clear "0" CY.

6. minus one instruction

DEC ADEC dataDEC @RiDEC Rn

The DEC instruction decrements the content of the pointed register by 1, and the result is still sent back to the original register. If the content of the original register is 00H, it will be FFH after decrementing 1. The operation result does not affect any flag bits. This group of instructions uses direct, register and inter-register addressing. Like the add 1 instruction, in the second instruction, if the direct address is an I/O port, a "read-modify-write" operation is performed.