06-S3C2440 learning: transplanting 2012u-boot to S3C2440 (transplantation process 1) creating a new board + modifying the clock + SDRAM + UART

Transplant u-boot-2012.04 to build a new board_clock_SDRAM_UART

(1) Create a new board directory and configure the header file

tar xjf u-boot-2012.04.01.tar.bz2

cd u-boot-2012.04.01

cd board/samsung/

cp smdk2410 smdk2440 –rf

cd ../..

cd /include/configs/

cp smdk2410.h smdk2440.h

(2) Modify boards.cfg:

Modeled after

smdk2410                     arm         arm920t     -                   samsung        s3c24x0

Add to:

smdk2440                     arm         arm920t     -                   samsung        s3c24x0 

vi command:

yy: copy the current line to the vi buffer

p: paste buffer

make  smdk2440_config

make

(3) Burn and check the result. If there is no output, make some adjustments.

Update source insight project

(4) Analyze the u-boot startup process

Start the analysis from start.S:

After reading the code, I found that the memory controller is set with 60MHZ clock calculation parameters in UBOOT, but MPLL is not set yet.

   Solution: Put the MPLL settings in start.S and cancel the MPLL settings in board_early_init_f

call_board_init_f:

ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)

bic sp, sp, #7 /* 8-byte alignment for ABI compliance */

ldr r0,=0x00000000

bl board_init_f

for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {

if ((*init_fnc_ptr)() != 0) {

hang ();

}

}

init_fnc_t *init_sequence[] = {

#if defined(CONFIG_ARCH_CPU_INIT)

arch_cpu_init, /* basic arch cpu dependent setup */

#endif

#if defined(CONFIG_BOARD_EARLY_INIT_F)

board_early_init_f,

#endif

#ifdef CONFIG_OF_CONTROL

fdtdec_check_fdt,

#endif

timer_init, /* initialize timer */

#ifdef CONFIG_FSL_ESDHC

get_clocks,

#endif

env_init, /* initialize environment */

init_baudrate, /* initialze baudrate settings */

serial_init, /* serial communications setup */

console_init_f, /* stage 1 init of console */

display_banner, /* say that we are here */

#if defined(CONFIG_DISPLAY_CPUINFO)

print_cpuinfo, /* display cpu info (and speed) */

#endif

#if defined(CONFIG_DISPLAY_BOARDINFO)

checkboard, /* display board info */

#endif

#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)

init_func_i2c,

#endif

dram_init, /* configure available RAM banks */

NULL,

};

board_early_init_f：

int board_early_init_f(void)

{

struct s3c24x0_clock_power * const clk_power =

s3c24x0_get_base_clock_power();

struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();

/* to reduce PLL lock time, adjust the LOCKTIME register */

writel(0xFFFFFF, &clk_power->locktime);

/* configure MPLL */

writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,

       &clk_power->mpllcon);

/* some delay between MPLL and UPLL */

pll_delay(4000);

/* configure UPLL */

writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,

       &clk_power->upllcon);

/* some delay between MPLL and UPLL */

pll_delay(8000);

change into:

（5）

Compile and generate a new uboot, re-run, and observe the serial port output

Debug uboot through openjtag to check whether SDRAM initialization is correct

Obviously the SDRAM is wrong, so we set the clock ourselves and modify the SDRAM initialization code.

(6) Modify the clock and copy the tested bare metal SDRAM content code to use:

Remove:

/* FCLK:HCLK:PCLK = 1:2:4 */

/* default FCLK is 120 MHz ! */

ldr r0, =CLKDIVN

mov r1, #3

str r1, [r0]

to:

/* 2. Set the clock */

ldr r0, =0x4c000014

// mov r1, #0x03;   // FCLK:HCLK:PCLK=1:2:4, HDIVN=1,PDIVN=1

mov r1, #0x05;   // FCLK:HCLK:PCLK=1:4:8

str r1, [r0]

/* If HDIVN is non-zero, the CPU's bus mode should be changed from "fast bus mode" to "asynchronous bus mode" */

mrc p15, 0, r1, c1, c0, 0 /* Read control register */ 

orr r1, r1, #0xc0000000 /* Set to "asynchronous bus mode" */

mcr p15, 0, r1, c1, c0, 0 /* Write control register */

#define S3C2440_MPLL_400MHZ     ((0x5c<<12)|(0x01<<4)|(0x01))

/* MPLLCON = S3C2440_MPLL_200MHZ */

ldr r0, =0x4c000004

ldr r1, =S3C2440_MPLL_400MHZ

str r1, [r0]

/* Start ICACHE */

mrc p15, 0, r0, c1, c0, 0 @ read control reg

orr r0, r0, #(1<<12)

mcr p15, 0, r0, c1, c0, 0   @ write it back

(7) The memory cannot be used normally. Use the previous configuration settings to modify it:

cpu_init_crit—》lowlevel_init—》

will be as follows:

SMRDATA:

    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))

    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))

    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))

    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))

    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))

    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))

    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))

    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))

    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))

    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

    .word 0x32

    .word 0x30

    .word 0x30

change into:

SMRDATA:  

.long 0x22011110 //BWSCON

.long 0x00000700 //BANKCON0

.long 0x00000700 //BANKCON1

.long 0x00000700 //BANKCON2

.long 0x00000700 //BANKCON3  

.long 0x00000700 //BANKCON4

.long 0x00000700 //BANKCON5

.long 0x00018005 //BANKCON6

.long 0x00018005 //BANKCON7

.long 0x008C04F4 // REFRESH

.long 0x000000B1 //BANKSIZE

.long 0x00000030 //MRSRB6

.long 0x00000030 //MRSRB7

(8) Upload new files, re-make, copy and execute

At this point, there is garbled output and the serial port configuration has a problem, but after testing, the memory has been set successfully.

(9) Serial port settings to solve the garbled code problem.

init_sequence--》serial_init--》

int serial_init(void)

{

return serial_init_dev(UART_NR);

}

serial_init_dev--》_serial_setbrg：

reg = get_PCLK() / (16 * gd->baudrate) - 1;

get_PCLK：

ulong get_HCLK(void)

{

struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();

#ifdef CONFIG_S3C2440

switch (readl(&clk_power->clkdivn) & 0x6) {

default:

case 0:

return get_FCLK();

case 2:

return get_FCLK() / 2;

case 4:

return (readl(&clk_power->camdivn) & (1 << 9)) ?

get_FCLK() / 8 : get_FCLK() / 4;

case 6:

return (readl(&clk_power->camdivn) & (1 << 8)) ?

get_FCLK() / 6 : get_FCLK() / 3;

}

#else

return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();

#endif

}

Garbled code, check the serial port baud rate settings, and find that CONFIG_S3C2440 is not defined in get_HCLK

    Solution: include/configs/smdk2440.h: remove CONFIG_S3C2410

                                          #define CONFIG_S3C2440

                                          //#define CONFIG_CMD_NAND

(10) Update the file and compile it. The following error occurs:

(11) Recompilation successful

Burn the old uboot first and restart the development board q –usb download

Note: At this time, uboot only supports booting from NOR flash

Enter your selection: q

usb 1 30000000

protect off all

erase 0 7ffff

cp.b 30000000 0 80000   

Re-power on, the output is as follows, the garbled problem is solved

U-Boot 2012.04.01 (Apr 18 2017 - 16:17:08)

CPUID: 32440001

FCLK:      400 MHz

HCLK:      100 MHz

PCLK:       50 MHz

DRAM:  64 MiB

WARNING: Caches not enabled

Flash: *** failed ***

### ERROR ### Please RESET the board ###

uboot executes successfully: At this point, the serial port, SDRAM, clock and other resources have been initialized successfully. uboot starts normally.