14. S3C2440 bare metal - MMU

14.1 MMU Introduction

14.1.1 MMU Features

　　The Memory Management Unit (MMU) is responsible for mapping virtual addresses to physical addresses and provides hardware-based memory access permission checks. Today's multi-user, multi-process operating systems use MMU to allow each user process to have its own independent address space.

　　The address mapping function allows each process to have an address space that "appears" to be the same, and the memory access permission check can protect the memory used by each process from being damaged by other processes.

　　S3C2440/2410 has the following features:

• ARM V4 compatible mapping length, domain, access permission checking mechanism

• 4 mapping lengths: segment (1MB), large page (64KB), small page (4KB), tiny page (1KB)

• Access permissions can be set for each segment

• Each sub-page (i.e. 1/4 of the mapped page) of a large page or a small page can have its own access permissions.

• 16 domains implemented in hardware

• Instruction TLB (64 entries), data TLB (64 entries)

• Hardware access page table (address mapping and permission checking are automatically performed by hardware)

• The entries in the TLB are replaced using a round-robin algorithm (also called a cyclic algorithm).

• Can invalidate the entire TLB

• You can invalidate individual TLB entries

• You can lock an entry in the TLB. The instruction TLB and data TLB are independent of each other.　　

　　Before a program is run, it is not necessary to load its entirety into memory. Instead, only the part to be run needs to be loaded into memory first. The rest of the program can be loaded from disk when needed. When the memory is exhausted, the temporarily unused part can be loaded out to disk.

　　In a 32-bit CPU system, the virtual memory address range is 0~0xFFFFFFFF. This address range is called the virtual address space, and an address in it is called a virtual address.

　　The physical address space and physical address correspond to the virtual address space and virtual address, which correspond to the actual memory.

　　The virtual address must eventually be converted to a physical address to read and write actual data. This is done by dividing the virtual address space and the physical address space into small spaces of the same size (called segments or pages), and then establishing a mapping relationship between the two types of small spaces. Since the virtual address space is much larger than the physical space, it is possible that multiple virtual address spaces are mapped to the same physical address space, or some virtual address spaces are not mapped to specific physical address spaces (they can be mapped when they are used).

• Three concepts of the address translation process on ARM CPU

• VA: Virtual Address, virtual address

• MVA: Modified Virtual Address, the changed virtual address

• PA：Physical Address, physical address

　　When the MMU is not enabled, all components including the CPU core, cache, MMU, and peripherals use physical addresses.

　　After starting the MMU, the CPU core sends out a virtual address VA; VA is converted to MVA for use by the cache and MMU, where MVA is converted to PA; finally, PA is used to read and write the actual device:

1. The CPU core only sees and uses the virtual address VA. As for how VA is finally implemented on the physical address PA, the CPU core does not care.

2. Caches and MMUs are also blind to VA; they use the MVA to convert to PA.

3. The actual device does not see VA and MVA, and the physical address PA is used when reading and writing them.

　　MVA is the virtual address seen by everything other than the CPU core

14.1.2 Address Mapping Process

　　There are two ways to convert a virtual address to a physical address: use a certain mathematical formula to convert or use a table to store the physical address corresponding to the virtual address. This type of table is called a page table. The page consists of entries; each entry stores the physical address corresponding to a virtual address and its access rights, or the address of the next level page table. The ARM CPU uses a table.

　　S3C2440/2410 uses at most two levels of page tables: only one level of page table is used when converting in segment (Section, 1MB) mode, and two levels of page table are used when converting in page mode.

　　There are three page sizes: large page (64KB), small page (4KB), and tiny page (1KB).

　　The entry is also called a "descriptor". There are segment descriptors, large page descriptors, small page descriptors, and tiny page descriptors. They are mainly used to save the starting physical address of the corresponding segment or page; coarse page descriptors and fine page descriptors are used to save the physical address of the secondary page table.

　　The conversion process is:

1. Find the entry in the first-level page table for a given virtual address

2. If this entry is a segment descriptor, the physical address is returned and the conversion ends.

3. Otherwise, if this entry is a secondary page table descriptor, continue to use the virtual address to find the next entry in this secondary page table.

4. If this second entry is a page descriptor, the physical address is returned and the translation is complete.

5. Other errors

　　TTB base represents the address of the first-level page table, which can be written into register C2 (called page table base register) of coprocessor CP15.

14.1.3 Permission Management　

　　The MMU protects segments and pages. The protection of segments and pages is caused by several factors. It is determined by the access control field of the domain and the AP field in the first-level descriptor or second-level descriptor, as well as the S (for system) and R (for rom) control bits of the C1 register.

　　The domain in the MMU refers to a collection of segments, large pages or small pages. ARM supports up to 16 domains, and the access control characteristics of each domain are controlled by two bits in register C3 in CP15. The format of register C3 in CP15 is as follows:

　　 Each two bits control the access control characteristics of a domain. The codes and corresponding meanings are as follows:

• When the control bit is 00, this domain has no access rights;

• When the control bit is 01, the attribute of the domain is the "user" domain;

• When its domain is the "user" domain, storage access permission control is determined by AP, S, and R.

• When the control bit is 11, the attribute of the domain is the "system" domain.

• When its domain is the "system" domain, the values ​​of AP, S, and R will be ignored, and the CPU (regardless of whether the CPU runs at the user level or the privileged level) can directly access the storage content without performing storage permission checks.

　　When the domain is the "user" domain, the specific rules for AP, S, and R to control access rights are as follows:

　　When the domain is the "user" domain, when the CPU runs at the "privileged level" or "user level", AP, S, R control the storage access rights of the segment or page;

　　for example:

　　When the domain is the "user" domain, when the CPU runs at the "user level", AP=00, S=1, R=0. From the table, we can see that the CPU has no access rights at this time.

　　When the domain is the "user" domain, when the CPU runs at the "privileged level", AP=00, S=1, R=0, here the CPU can only read the storage content but cannot write. If it writes, an error will occur;

　　Note: The role of AP, S, and R in determining access rights is only used when their domain is the "user" domain.

14.2 Programming Address Mapping

　　The CPU core only cares about issuing addresses and reading and writing data. It does not care whether it is a virtual address or a physical address. The device behind it cares about what the address is.

　　When writing a program, the link address is not divided into physical address and virtual address. It is just a simple address. The link address is what the CPU sees.

• MMU Operation:

• Create an address mapping table, that is, establish a mapping from virtual address to physical address

• Tell the MMU the table address, that is, tell the MMU the memory address

• Start the MMU

　　mmu.lds

1 SECTIONS { 

2 first 0x00000000 : { head.o init.o }

3 second 0xB0004000 : AT(2048) { leds.o }

4 } 

　　head.S

 1 @*************************************************************************

 2@File:head.S

 3 @ Function: Set up SDRAM, copy the second part of the code to SDRAM, set up the page table, start the MMU,

 4 @ Then jump to SDRAM to continue execution

 5 @*********************************************************************************       

 6 

 7.text

 8. global_start

 9 _start:

10 ldr sp, =4096 @ Set the stack pointer. The following are all C functions. Before calling, you need to set the stack to point to the top of SRAM.

11 bl disable_watch_dog @ Turn off WATCHDOG, otherwise the CPU will restart continuously

12 bl memsetup @ Set up the memory controller to use SDRAM

13 bl copy_2th_to_sdram @ Copy the second part of the code to SDRAM

14 bl create_page_table @ Set the page table

15 bl mmu_init @ Start MMU

16 ldr sp, =0xB4000000 @ Reset the stack pointer to the top of SDRAM (using virtual address)

17 ldr pc, =0xB0004000 @ Jump to SDRAM and continue to execute the second part of the code

18 halt_loop:

19 b halt_loop

　　init.c

  1 /*

  2 * init.c: do some initialization, run in Steppingstone

  3 * It and head.S belong to the first part of the program. At this time, MMU is not turned on and physical address is used

  4 */ 

  5 

  6 /* WATCHDOG register */

  7 #define WTCON (*(volatile unsigned long *)0x53000000)

  8 /* Storage controller register start address */

  9 #define MEM_CTL_BASE 0x48000000

 10 

 11 

 12 /*

 13 * Turn off WATCHDOG, otherwise the CPU will restart continuously

 14 */

 15 void disable_watch_dog(void)

 16 {

 17 WTCON = 0; // Turning off WATCHDOG is very simple, just write 0 to this register

 18 }

 19 

 20 /*

 21 * Set up the memory controller to use SDRAM

 twenty two */

 23 void memsetup(void)

 twenty four {

 25 /* Values ​​of SDRAM 13 registers */

 26 unsigned long const mem_cfg_val[]={ 0x22011110, //BWSCON

 27 0x00000700, //BANKCON0

 28 0x00000700, //BANKCON1