14. S3C2440 bare metal - MMU

 29 0x00000700, //BANKCON2

 30 0x00000700, //BANKCON3  

 31 0x00000700, //BANKCON4

 32 0x00000700, //BANKCON5

 33 0x00018005, //BANKCON6

 34 0x00018005, //BANKCON7

 35 0x008C07A3, //REFRESH

 36 0x000000B1, //BANKSIZE

 37 0x00000030, //MRSRB6

 38 0x00000030, //MRSRB7

 39 };

 40 int i = 0;

 41 volatile unsigned long *p = (volatile unsigned long *)MEM_CTL_BASE;

 42 for(; i < 13; i++)

 43 p[i] = mem_cfg_val[i]; //In a 32-bit CPU, the pointer moves 4 bytes at a time

 44 }

 45 

 46 /*

 47 * Copy the second part of the code to SDRAM

 48 */

 49 void copy_2th_to_sdram(void)

 50 {

 51 unsigned int *pdwSrc = (unsigned int *)2048; //The link script specifies that the storage address of led.o is 2048

 52 unsigned int *pdwDest = (unsigned int *)0x30004000; // The address where led.o is stored in SDRAM 

 53     

 54 while (pdwSrc < (unsigned int *)4096)

 55 {

 56 *pdwDest = *pdwSrc;

 57 pdwDest++;

 58 pdwSrc++;

 59 }

 60 }

 61 

 62 /*

 63 * Set up page table

 64 */

 65 void create_page_table(void)

 66 {

 67 

 68 /* 

 69 * Some macro definitions for segment descriptors

 70 */ 

 71 #define MMU_FULL_ACCESS (3 << 10) /* Access rights*/

 72 #define MMU_DOMAIN (0 << 5) /* Which domain does it belong to */

 73 #define MMU_SPECIAL (1 << 4) /* must be 1 */

 74 #define MMU_CACHEABLE (1 << 3) /* cacheable */

 75 #define MMU_BUFFERABLE (1 << 2) /* bufferable */

 76 #define MMU_SECTION (2) /* Indicates that this is a segment descriptor*/

 77 #define MMU_SECDESC (MMU_FULL_ACCESS | MMU_DOMAIN | MMU_SPECIAL |

 78 MMU_SECTION)

 79 #define MMU_SECDESC_WB (MMU_FULL_ACCESS | MMU_DOMAIN | MMU_SPECIAL |

 80 MMU_CACHEABLE | MMU_BUFFERABLE | MMU_SECTION)

 81 #define MMU_SECTION_SIZE 0x00100000

 82 

 83 unsigned long virtuladdr, physicaladdr;

 84 unsigned long *mmu_tlb_base = (unsigned long *)0x30000000;

 85     

 86 /*

 87 * The starting physical address of Steppingstone is 0, and the starting running address of the first part of the program is also 0.

 88 * In order to run the first part of the program after turning on MMU,

 89 * Map virtual addresses from 0 to 1M to the same physical address

 90 */

 91 virtuladdr = 0;

 92 physicaladdr = 0;

 93 *(mmu_tlb_base + (virtuladdr >> 20)) = (physicaladdr & 0xFFF00000) |

 94 MMU_SECDESC_WB;

 95 

 96 /*

 97 * 0x56000000 is the starting physical address of the GPIO register.

 98 * The physical addresses of the two registers GPBCON and GPBDAT are 0x56000050 and 0x56000054,

 99 * In order to operate GPFCON and GPFDAC at addresses 0xA0000050 and 0xA0000054 in the second part of the program,

100 * Map the 1M virtual address space starting from 0xA0000000 to the 1M physical address space starting from 0x56000000

101 */

102 virtuladdr = 0xA0000000;

103 physicaladdr = 0x56000000;

104 *(mmu_tlb_base + (virtuladdr >> 20)) = (physicaladdr & 0xFFF00000) |

105 MMU_SECDESC;

106 

107 /*

108 * The physical address range of SDRAM is 0x30000000～0x33FFFFFF,

109 * Map virtual address 0xB0000000~0xB3FFFFFF to physical address 0x30000000~0x33FFFFFF,

110 * 64M in total, involving 64 segment descriptors

111 */

112 virtuladdr = 0xB0000000;

113 physicaladdr = 0x30000000;

114 while (virtuladdr < 0xB4000000)

115 {

116 *(mmu_tlb_base + (virtuladdr >> 20)) = (physicaladdr & 0xFFF00000) |

117 MMU_SECDESC_WB;

118 virtuladdr += 0x100000;

119 physicaladdr += 0x100000;

120 }

121 }

122 

123 /*

124 * Start MMU

125 */

126 void mmu_init(void)

127 {

128 unsigned long ttb = 0x30000000;

129 

130 __asm__(

131 "mov r0, #0n"

132 "mcr p15, 0, r0, c7, c7, 0n" /* Invalidate ICaches and DCaches */

133     

134 "mcr p15, 0, r0, c7, c10, 4n" /* drain write buffer on v4 */

135 "mcr p15, 0, r0, c8, c7, 0n" /* Invalidate instruction and data TLB */

136     

137 "mov r4, %0n" /* r4 = page table base address*/

138 "mcr p15, 0, r4, c2, c0, 0n" /* Set the page table base address register */

139     

140 "mvn r0, #0n"                   

141 "mcr p15, 0, r0, c3, c0, 0n" /* The domain access control register is set to 0xFFFFFFFF,

142 * No permission check 

143 */    

144 /* 

145 * For the control register, first read its value, and then modify the bits of interest based on this.

146 * Then write

147 */

148 "mrc p15, 0, r0, c1, c0, 0n" /* Read the value of the control register */

149     

150 /* The lower 16 bits of the control register mean: .RVI ..RS B... .CAM

151 * R: Indicates the algorithm used when swapping out entries in the Cache.

152 * 0 = Random replacement; 1 = Round robin replacement

153 * V : indicates the location of the exception vector table.

154 * 0 = Low addresses = 0x00000000; 1 = High addresses = 0xFFFF0000

155 * I : 0 = disable ICaches; 1 = enable ICaches

156 * R, S: Used together with the descriptor in the page table to determine the access rights of memory

157 * B : 0 = CPU is in little endian; 1 = CPU is in big endian

158 * C : 0 = disable DCaches; 1 = enable DCaches

159 * A : 0 = No address alignment check is performed during data access; 1 = Address alignment check is performed during data access

160 * M : 0 = disable MMU; 1 = enable MMU

161 */

162     

163 /*  

164 * Clear the unneeded bits first, and reset them later if needed    

165 */

166 /* .RVI ..RS B... .CAM */ 

167 "bic r0, r0, #0x3000n" /* ..11 .... .... .... Clear V, I bits*/

168 "bic r0, r0, #0x0300n" /* .... ..11 .... .... Clear R, S bits*/

169 "bic r0, r0, #0x0087n" /* .... .... 1... .111 Clear B/C/A/M */

170 

171 /*

172 * Set the required bit

173 */

174 "orr r0, r0, #0x0002n" /* .... .... .... ..1. Enable alignment check*/

175 "orr r0, r0, #0x0004n" /* .... .... .... .1.. Enable DCaches */

176 "orr r0, r0, #0x1000n" /* ...1 .... .... .... Enable ICaches */

177 "orr r0, r0, #0x0001n" /* .... .... .... ...1 Enable MMU */

178     

179 "mcr p15, 0, r0, c1, c0, 0n" /* Write the modified value to the control register */

180 : /* No output */

181 : "r" (ttb) );

182 }