Detailed explanation of LPCXpresso54628, a low-power MCU based on ARM Cortex-M4 core

NXP's LPCXpresso54628 is a low-power MCU based on the ARM Cortex-M4 core, with rich peripherals, very low power consumption and enhanced debugging features. The ARM Cortex-M4 CPU adopts a 3-stage pipeline, a Harvard architecture with separate local instruction and data buses and a third bus for peripherals, supports single-cycle digital signal processing and SIMD instructions, and the core also integrates a hardware floating-point processor. The LPC546xx series includes 512KB flash memory, 200KB SRAM, up to 16kB EEPROM, four SPI flash interfaces (SPIFI), high-speed and full-speed USB host and device controllers, Ethernet AVB, LCD controller, smart card interface, SD/MMC, CAN FD and external memory controller (EMC), DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTImer/PWM, RTC/alarm timer, multi-rate timer (MRT), window watchdog timer (WWDT), ten flexible serial notification and criticism communication peripherals (USART, SPI, I2S, I2C interface), secure hash algorithm (SHA), 12-bit 5.0MSPS ADC and temperature sensor. Mainly used in embedded applications. This article introduces the main features and block diagram of the LPCXpresso546xx series, as well as the main features and circuit diagram of the LPCXpresso546xx evaluation board.

The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embeddedpplicaTIons featuring a rich peripheral set with very low power consumption and enhanced debug features.The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated into the core.

The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals(USART, SPI, I2S, I2C interface), Secure Hash Algorithm (SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.

LPCXpresso54628 main features:

 ARM Cortex-M4 core (version r0p1):
 ARM Cortex-M4 processor, running at a frequency of up to 220 MHz.
 The LPC5460x/61x devices operate at CPU frequencies of up to 180 MHz. The
LPC54628 device operates at CPU frequencies of up to 220 MHz.
 Floating Point Unit (FPU) and Memory Protection Unit (MPU).
 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
 Non-maskable Interrupt (NMI) input with a selection of sources.
 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,and four watch points. Includes Serial Wire Output and ETM Trace for enhanceddebug capabilities, and a debug timestamp counter.
 System tick timer.
 On-chip memory:
 Up to 512 KB on-chip flash program memory with flash accelerator and 256 bytepage erase and write.
 Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and anadditional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USBtraffic.
 16 KB of EEPROM.
 ROM API support:
 Flash In-Application Programming (IAP) and In-System Programming (ISP).
 ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.
 Booting from valid user code in flash, USART, SPI, and I2C.
 Legacy, Single, and Dual image boot.
 OTP API for programming OTP memory.
 Random Number Generator (RNG) API.
 Serial interfaces:
 Flexcomm Interface contains up to ten serial peripherals. Each Flexcomm Interface can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. Avariety of clocking options are available to each Flexcomm Interface and include ashared fractional baud-rate generator.
 I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of trueI2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
 Two ISO 7816 Smart Card Interfaces with DMA support.
 USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
 USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMAcontroller supporting crystal-less operation in device mode.
 SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
 Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller.
 Two CAN FD modules with dedicated DMA controller.
 Digital peripherals:
 DMA controller with 30 channels and up to 24 programmable triggers, able toaccess all memories and DMA-capable peripherals.
 LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-FilmTransistor (TFT) displays. It has a dedicated DMA controller, selectable displayresolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
 External Memory Controller (EMC) provides support for asynchronous staticmemory devices such as RAM, ROM and flash, in addition to dynamic memoriessuch as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC buswidth (bit) on LQFP100 and TFBGA100 packages supports up to 8/16 data linewide static memory, in addition to dynamic memories, such as, SDRAM (2 banksonly) with an SDRAM clock of up to 100 MHz.
 Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
 CRC engine block can calculate a CRC on supplied data using one of threestandard polynomials with DMA support.
 Up to 171 General-Purpose Input/Output (GPIO) pins.
 GPIO registers are located on the AHB for fast access. The DMA supports GPIOports.
 Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,falling or both input edges.
 Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical(AND/OR) combination of input states.
 CRC engine.
 Analog peripherals:
 12-bit ADC with 12 input channels and with multiple internal and external trigger
inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two
independent conversion sequences.
 Integrated temperature sensor connected to the ADC.
 DMIC subsystem including a dual-channel PDM microphone interface, flexible
decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection,and the option to stream the processed output data to I2S.
 Timers:
 Five 32-bit general purpose timers/counters, four of which support up to fourcapture inputs and four compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests. The fifth timerdoes not have external pin connections and may be used for internal timingoperations.
 SCTimer/PWM with 8 input and 10 output functions (including capture and match).
Inputs and outputs can be routed to/from external pins and internally to or fromselected peripherals. Internally, the SCTimer/PWM supports 10 match/captures, 10events, and 10 states.
 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on powerdomain. A timer in the RTC can be used for wake-up from all low power modesincluding deep power-down, with 1 ms resolution.
 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation atup to four programmable, fixed rates.
 Windowed Watchdog Timer (WWDT).
 Repetitive Interrupt Timer (RIT) for debug time stamping and for general purposeuse.
 Security features:
 enhanced Code Read Protection (eCRP) to protect user code.
 OTP memory for ECRP settings, and user application specific data.
 Secure Hash Algorithm (SHA1/SHA2) module with dedicated DMA controller.
 Clock generation:
 12 MHz internal Free Running Oscillator (FRO). This oscillator provides aselectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from theselected higher frequency) that can be used as a system clock. The FRO istrimmed to +/-1 % accuracy over the entire voltage and temperature range.
 External clock input for clock frequencies of up to 25 MHz.
 Crystal oscillator with an operating range of 1 MHz to 25 MHz.
 Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.
 32.768 kHz low-power RTC oscillator.
 System pll allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHzRTC oscillator.
 Two additional PLLs for USB clock and audio subsystem.
 Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
 Clock output function with divider.
 Frequency measurement unit for measuring the frequency of any on-chip oroff-chip clock signal.
 Power control:
 Programmable PMU (Power Management Unit) to minimize power consumptionand to match requirements at different performance levels.
 Reduced power modes: sleep, deep-sleep, and deep power-down.
 Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2Cperipherals when operating as slaves.
 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can beused to wake up the device from low power modes.
 Power-On Reset (POR).
 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
 Single power supply 1.71 V to 3.6 V.
 Power-On Reset (POR).
 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
 JTAG boundary scan supported.
 128 bit unique device serial number for identification.
 Operating temperature range -40 ℃ to +105 ℃.
 Available in TFBGA180, TFBGA100, LQFP208, and LQFP100 packages