Design of industrial CT motion control system using embedded ARM+FPGA

1 Introduction

The motion control system of an industrial CT machine often requires precise and real-time control of the motion of multiple axes. In the past, the motion controller was designed using an industrial computer + multiple boards. As the overall functions of industrial CT machines become increasingly complex, the overall system has increasingly stringent requirements on the size, cost, and power consumption of the motion control system. On the other hand, the number of axes controlled by the motion control system is increasing, the control accuracy requirements are becoming higher and higher, and the real-time requirements of the controlled objects are becoming stronger and stronger.

The existing control system consisting of industrial computers and multiple boards gradually shows disadvantages in motion control. The ARM+FPGA hardware solution frees the industrial computer from the existing motion control system and replaces it with a small, low-power, and powerful ARM processor. The powerful embedded Linux operating system ensures that the functions of the ARM processor can be brought into full play.

2 Design and implementation of key technologies of hardware system

This system uses the ARM+FPGA structure to design the motion control system. Compared with the commonly used IPC (Industrial Personal Computer) + board motion control system, it has the following advantages:

(1) FPGA is used to complete the detailed tasks of motion control and realize the design concept of hardware softening. It has the characteristics of software programmability and reconfigurability, and the advantages of hardware high performance, high reliability and high consistency.

(2) Compared with the existing IPC+board structure, the embedded application solution has great advantages in terms of size, cost and performance.

(3) FPGA has high-speed parallel execution capabilities, and the real-time performance of the system is greatly improved.

(4) Package the drivers for operating the underlying hardware in ARM to facilitate application calls and complete secondary development for users more quickly.

2.1 Overall design of hardware system

The structure of the industrial CT motion control system is shown in Figure 1. The system is based on Atmel's ARM9 core processor AT91RM9200 and Altera's Cyclone series chip EP1C6Q240C8. As the main control chip, ARM9 is responsible for the control of the entire system. It coordinates data exchange with FPGA through the AHB[3] bus and sends the received data to the industrial control computer through the network for image processing and reconstruction. FPGA is responsible for receiving serial data from the data acquisition system and converting it into parallel data and storing it in the FPGA's RAM. At the same time, it sends an interrupt request response to ARM to notify ARM9 to read. AT91RM9200, SDRAM, FLASH, power supply and other basic peripheral circuits constitute the minimum system for embedded Linux operation, while the FPGA minimum system consists of EP1C6Q240C8, clock circuit, configuration interface, etc. Then the two are connected through the high-speed AHB bus to achieve fast data transmission.

Figure 1 Industrial CT motion control system structure diagram

2.2 ARM and FPGA interface design

In the system, ARM is used as a general-purpose processor to implement functions such as triggering system tasks, sending system commands, and scheduling tasks.

As an ARM peripheral, FPGA is used to parse the commands sent by ARM via the address data bus, and finally complete the functions of pulse sending and pulse counting as well as specific motion control details according to the requirements of ARM commands.

The two FPGAs are connected to the address/data bus of ARM through their respective address/data buses, and the two sides can exchange data bidirectionally.

ARM and FPGA are connected through the address selection signal line. The two FPGAs each serve as a peripheral chip of ARM and run in an independent address space. The address selection signal is combined with the address bus to enable ARM to address the internal registers of FPGA.

3 Design and implementation of key technologies of software system

The system software is designed with a layered concept. The entire system software is mainly composed of the host operating system, host development software, target board operating system, target board underlying hardware driver, target board application, and HDL hardware description language. The host operating system selects REDHAT-LINUX9.0 version; the host development software mainly consists of some cross-compilation environments, assembly and linking tools; the target board operating system selects ARM-LINUX operating system; the target board application is written in C code; HDL language is used to describe the functions of FPGA.

The software system hierarchical diagram is shown in Figure 2. In the host machine, the cross-compiler expands the application code and the underlying hardware driver code to be run on the target board platform, and then passes them to the target board through the hardware interface between the host machine and the target board. The target board controls the various function registers configured in the FPGA module through the underlying hardware driver to complete the specific control task. This article focuses on the design of the internal functional module of the FPGA and the driver interface design.

Figure 2 Schematic diagram of software system layering

3.1 Design of key functional modules inside FPGA

FPGA is not good at computing data, but this system needs to perform corresponding operations for the control of each axis. Therefore, in the design of each axis control module, try not to involve complex algorithm implementation, and leave the algorithm part to ARM for processing. In principle, FPGA only receives data processed by ARM, and then processes it according to the processing results of the ARM main control unit.

The block diagram of the single-axis control module is shown in Figure 3. Two counters are configured in each position management unit: a logical position counter and an actual position counter. The input end of the logical position counter is connected to the output end of the pulse generator, and its function is to measure the number of pulses actually sent from the pulse generator. The input end of the actual position counter is connected to the output end of the encoder , and its function is to measure the number of pulses sent from the encoder. The logical position register and the actual position register actually constitute a closed-loop system, the former is the input of the closed-loop system, and the latter is the output of the closed-loop system. When the error range of the two does not exceed a certain limit, the real-time pulse sending rate is adjusted in the FPGA; when the error of the two exceeds a certain set range, the FPGA sends an interrupt request to the ARM. When an axis receives a deceleration signal SD or an extreme position signal EL, an interrupt is sent to the ARM through the same interrupt generator module inside the FPGA. After receiving the interrupt signal, the ARM starts the motion control process, adjusts the PID control parameters, and calculates the control amount .

Figure 3 Single-axis control module design

3.2 Driver Interface Design

In the system design, two FPGAs are used as ARM peripherals and are mounted in the ARM peripheral address space. When ARM wants to access FPGA, it must first run the instruction containing the address space address of FPGA in ARM, and then the chip select line of ARM selects FPGA. FPGA detects that it has been selected and starts to detect the address data contained in the ARM instruction transmitted on the address bus. According to the data on the address bus transmitted from the ARM address line, FPGA reads the data on the data bus transmitted from the ARM data bus, and then starts to perform corresponding actions, thus completing a control task. Registers are one of the basic components of this motion control system. ARM's control of FPGA is realized by configuring registers inside FPGA. The overall structure of the configured FPGA is shown in Figure 4.

Figure 4 FPGA internal structure diagram

4 Control Algorithm Design and Simulation

4.1 Single neuron adaptive PID controller design

The structure of the single neuron adaptive PID controller is shown in Figure 5.

Figure 5 Single neuron adaptive PID controller

In Figure 5, the three state variables of the neuron are:

The single neuron adaptive controller realizes the adaptive and self-learning functions by adjusting the weight coefficients. The adjustment of the weight coefficients is realized according to the supervised Hebb learning rule.

The output of the controller is:

in:

In formula (5), w'i is the weighting coefficient, which can be modified online. The online learning of the weighted value adopts a standardized learning algorithm, and the formula is formula (6):

In formula (7), ηi (i = I, P, D), ηI, ηP, ηD are the learning rates of integration, proportion, and differentiation, respectively.

4.2 Algorithm Simulation

Parameters of the simulation system: the learning rates of the proportional, integral and differential are ηP = 0.40, ηI = 0.35, ηD = 0.40 respectively, the initial error value of the system is set to 1, and the simulation curve is shown in Figure 6. From the simulation results, it can be seen that the system PID control parameters are adjusted online with the operation of the system, and the system is controlled by the adjusted PID parameters, and the system error eventually tends to 0.

Figure 6 Single neuron PID control error curve

5 Operation Results

5.1 System displacement debugging results

In order to test the position control effect of the motion control system, 100 tests were conducted when the motor was unloaded. Figure 7 shows the displacement test result curve of the motor when it was unloaded measured in the laboratory. Each test data is the average value of 100 test data. Figure 7 is the curve fitting diagram of each experimental data. It can be seen from the figure that the error curve of the pulse generator and the pulse counter has undergone an accumulation process when the motor is unloaded. When the error exceeds the set value of 0.18%, the single neuron adaptive PID controller starts to adjust the PID control parameters online. The adjustment result makes the system error approach 0.