Implementation of FPGA Embedded System Based on ARM

ARM (Advanced RISC Machines) can be considered a company, a general term for a type of microprocessor, or a technology. Microprocessor applications based on ARM technology account for more than 75% of the market share of 32-bit RISC microprocessors, and ARM technology is gradually penetrating into every aspect of people's lives [1]. So far, ARM microprocessors and technologies have been widely used in various fields, including industrial control, network applications, consumer electronics, imaging and security products, etc.

FPGA (Field Programmable Gate Array) is a high-density field programmable logic device, whose logic functions are realized by configuring the data files generated by the design into the static configuration data memory (SRAM) inside the device. FPGA is reprogrammable and can flexibly realize various logic functions.

FPGA based on SRAM technology is volatile. After the system loses power, its internal configuration data is easily lost, so an external ROM is required to save its configuration data. After the system is powered on, the data must be reconfigured to work properly. There are currently two solutions. One is to use a dedicated PROM. Taking Xilinx's FPGA, XCFxx series PROM as an example, it can provide the configuration timing of the FPGA and automatically load the configuration data in the PROM into the SRAM of the FPGA when powered on; the other is to use other non-volatile memories such as E2PROM and Flash to store configuration data in a system containing a microprocessor (such as an embedded system). The microprocessor simulates the configuration timing of the FPGA to place the data in the ROM into the FPGA. Compared with the first solution, this solution saves costs and reduces the system size. It is suitable for systems with stringent requirements on cost and size.

In the design of portable virtual instrument, embedded system and FPGA are used to realize system functions. The embedded microprocessor adopts Samsung's ARM7TDMI series processor S3C44BOX: FPGA adopts Xilinx's Spartan-3E series XC3S100E, and S3C44BOX is used to complete the configuration of XC3S100E. Good results have been achieved.

2 Principles of slave configuration

2.1 Principle of slave string configuration

Xilinx's Spartan-3E series FPGA products are 2.5 V low-voltage FPGA devices using 90 nm technology.

The XC3S100E is a Spartan-3E series FPGA with a total gate count of 100,000 gates. It can be configured in slave-serial, master-serial, slave-parallel, master-parallel, and JTAG modes [2]. The main pin functions of the XC3S100E related to the slave-serial configuration mode are as follows:

M[2:0]: Configuration mode selection. M2, M1, and M0 are all connected to pull-up resistors, that is, when M[2:0]: 111, it is slave mode;

CCLK: Configuration clock, the microprocessor provides the clock source, and the rising edge is valid:

DIN: Serial configuration data input:

DOUT: Serial data output, used for daisy-chain configuration:

PROG_B: Low level asynchronously resets the internal logic of the FPGA. Internally configurable: After the memory is completely reset, this pin indicates a high level.

When this pin is high, the FPGA can be configured:

INIT_B: When it jumps from low level to high level, it samples the configuration mode, that is, the value of M[2:0] determines the configuration mode; if a configuration error occurs during the configuration process, INIT_B will be low level;

DONE: Low level during reset. High level if configuration is successful.

2.2 Microprocessor Slave Configuration: FPGA Timing

The FPGA configuration process is as follows:

After the system is powered on, pull PROG_B low to reset the FPGA internal logic and reconfigure the FPGA. After the internal logic is fully reset (about 100μs), set PROG_ high.

INIT_B is low level, PROG_B is pulled high and kept for 300 ns, then FPGA sets INIT_B high. At the moment when INIT_B jumps from low to high, the configuration mode M[2:0] is sampled. This system adopts the slave serial configuration mode.

After the FPGA sampling configuration mode, the microprocessor can configure the clock CCLK and data to the FPGA. At the rising edge of CCLK, the data is transmitted to DIN. The data byte is sent low first and then high. If an error occurs during the configuration process, INIT_B is low.

All configuration data transmission is completed and CRC check is correct. Then DONE is high level, otherwise it is low level.

When DONE is high, the FPGA releases the global tri-state (GTS), activates the I/O pins, releases all set resets (GSR) and global write enable (GWE), and starts executing the logic in the configuration area.

The timing of the microprocessor configuring the FPGA from the serial is shown in Figure 1.

2.3 How to generate configuration files

Using the development tool ISE8.1 provided by Xilinx, programming files can be generated after synthesis, mapping, layout and routing. The programming files contain .bit, .bin, .mcs, .tek, .hex and other formats. Among them, the .bit format is used for JTAG download, and the other formats are used for special PROM programming. First, generate a .bin file according to the method of generating a special PROM programming file. Then convert the .bin file into the storage form of an ASCⅡ code file, and separate each byte with a comma. Then store the configuration data in the array config_data_array[] of a header file of the system program as part of the system program source code and compile it with other programs.

3 Hardware Design

The embedded microprocessor S3C44BOX has an ARM7TDMI core and integrates a rich set of peripheral function modules. The internal 8 kB Cache greatly improves performance. S3C44BOX can access 256MB of address space and has a maximum operating frequency of 66 MHz. 4 MB Flash is used as program memory, which can be used to store the code running the system. The XC3S100E slave serial configuration program and configuration file are both solidified and saved in it. The Flash supports low voltage (1.65 V ~ 3.3 V) write operations. The 8 MB SDRAM is the program running space, which directly runs the code in the Flash, but the speed is very slow. Usually, the code in the Flash is moved to the SDRAM. S3C44BOX and XC3S100E are mainly connected through 5 signal lines: PROG_B, INIT_B, DONE, CCLK, and DIN, as shown in Figure 2. Among them, VCC33 represents 3.3 V and VCC25 represents 2.5 V.

4 Software Design

The software design process is shown in Figure 3. The programming of the configuration software must ensure that ARM works completely according to the timing of the configuration signal. The key issue is

It uses the general I/O ports GPF0, GPF1, GPF2, GPF3, and GPF4 of S3C44BOX to simulate the timing of DIN, CCLK, DONE, INIT_B, and PROG_B.

In S3C44BOX, most pins are multi-function pins, and the corresponding pin functions can be selected through the port configuration register.

Taking port F as an example, the control register rPCONF is used to set the input, output or special function of the pin; the data register rPDATF[0:8] corresponds to the data on the GPF0~GPF8 pins. Each bit of the read-write register rPDATF corresponds to the read or write of the pin. For example, the CCLK rising edge timing is obtained by writing 0 to GPF1 first and then writing 1, and the delay program is implemented by the for loop.

Then keep waiting in a loop

CCLK puts 1 bit of data into DIN at each rising edge. First, set GPF1 low, prepare 1 bit of data in GPF0, and then set GPF1 high. In this way, each byte in config_data_array[] is written into the FPGA in the order of low bit first and high bit later.

The size of Xilinx's FPGA configuration files is the same, regardless of the complexity of the FPGA's internal logic design. Taking the 100,000-gate FPGA XC3S100E of the Spartan_3E series as an example, its configuration file is fixed to 581,344 bits. If the CCLK clock period is set to 2μs, the configuration time is about 1.2 s.

5 Experimental results verification

Verification environment: The hardware uses the self-developed experimental board and Wuhan Chuangwei's JTAG hardware emulator; the software uses Xilinx's development tool ISE8.1 and Wuhan Chuangwei's integrated development environment ADT 1000 (supporting ARM7, ARM9).

Use Verilog HDL to write the program led.v to display 0~F on the seven-segment digital tube in a loop. Use ISE8.1 to compile, synthesize, map, and place and route. Generate the led.bin file for programming the dedicated PROM. Use a simple C program to convert the .bin file into an ASCII code file, and then copy the ASCII code file to the configuration data array config_data_array[]. Then compile the configuration program, configuration data, and system program in the ADT environment, and burn the generated .bin file into the Flash through the JTAG port. After powering on again, the FPGA configuration is normal, and the experimental results are consistent with the preset.

6 Conclusion

The FPGA slave configuration scheme based on ARM has a simple structure, easy wiring, and simple software programming, which is very suitable for embedded system design. Although the control circuit is designed for Xilinx's Spartan-3E series FPGA, it can be used for other series of FPGA devices with slight modifications, so it has a certain versatility. In addition, since FPGA has the flexibility of repeatable configuration, in embedded systems, Flash can be remotely burned through serial ports and network ports to reconstruct system functions. This online reconstruction technology makes it possible for intelligent online maintenance, functional reorganization and online upgrades of equipment, and it is very flexible. The scheme proposed in this article has reference significance for digital system design and has broad application prospects.