1. Storage Controller Introduction
The "Storage Manager" in s3c2440 provides the signals needed to access external devices and has the following features:
1. Support little endian and big endian (selected by software)
2. Each bank is 128M, there are 8 banks in total, totaling 1G
3.BANK0~BANK5 can support external ROM, SRAM, etc. BANK6~BANK7 can support SDRAM in addition to ROM and SRAM
4. The starting address of BANK0~BANK7 is fixed
5. When connected to external SDRAM, supports self-refresh and power saving mode
The access range of ADDR0~ADDR26 on s3c2440 is only 128M. How to reach the above 1G? Through the 8 chip select signals nGCS0-nGCS7 led out to the outside, corresponding to BANK0~BANK7. The chip select signal output low level can select the corresponding external device.
2. Experimental code
The experimental process:
Disable the watchdog timer—>Copy the first 4k bytes in the nand flash to the internal SRAM of the chip for execution—>Initialize the external SDRAM through the storage controller—>Copy the code to the SDRAM—>Jump to the SDRAM for execution.
The following are the relevant registers that need to be configured for the storage controller. You need to read the manual:
0x22011110, //BWSCON
0x00000700, //BANKCON0
0x00000700, //BANKCON1
0x00000700, //BANKCON2
0x00000700, //BANKCON3
0x00000700, //BANKCON4
0x00000700, //BANKCON5
0x00018005, //BANKCON6
0x00018005, //BANKCON7
0x008C07A3, //REFRESH
0x000000B1, //BANKSIZE
0x00000030, //MRSRB6
0x00000030, //MRSRB7
head.S
.equ MEM_CTL_BASE, 0x48000000 //.euq A B is A=B, which is equivalent to the macro definition of C language
.equ SDRAM_BASE, 0x30000000
.text
.global _start
_start:
bl disable_watch_dog
bl memsetup //Set up the storage controller
bl copy_steppingstone_to_sdram //Copy code to SDRAM
ldr pc, =on_sdram //jump to SDRAM for execution
on_sdram:
ldr sp, =0x34000000 //Set up the stack
bl main
halt_loop:
b halt_loop
disable_watch_dog:
mov r1, #0x53000000
mov r2, #0x0
str r2, [r1] //turn off the watchdog
mov pc, lr //return
copy_steppingstone_to_sdram:
mov r1, #0x0
ldr r2, =SDRAM_BASE
mov r3, #4*1024
1:
ldr r4, [r1], #4
str r4, [r2], #4
cmp r1, r3
bne 1b //bne b jumps ne is not equal, which means if they are not equal, jump to 1 to continue execution. Note that 1 is not l. . .
mov pc, lr
memsetup:
mov r1, #MEM_CTL_BASE
adrl r2, mem_cfg_val
add r3, r1, #52
1:
ldr r4, [r2], #4
str r4, [r1], #4
cmp r1, r3
bne 1b
mov pc, lr
.align 4
mem_cfg_val: //The value of 13 registers in the storage controller
.long 0x22011110
.long 0x00000700
.long 0x00000700
.long 0x00000700
.long 0x00000700
.long 0x00000700
.long 0x00000700
.long 0x00018005
.long 0x00018005
.long 0x008C07A3
.long 0x000000B1
.long 0x00000030
.long 0x00000030
Makefile
sdram.bin:head.S led.c
arm-linux-gcc -c head.S -o head.o
arm-linux-gcc -c led.c -o led.o
arm-linux-ld -Ttext 0x30000000 head.o led.o -o sdram_elf
arm-linux-objcopy -O binary -S sdram_elf sdram.bin
arm-linux-objdump -D -m arm sdram_elf > sdram.dis
clean:
rm -rf *.o *.bin *.dis *elf
The led.c used for testing can be any of the LED lighting programs in the previous article.
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