Playing with Zynq Serial 37——[ex56] AXI HP bus reading and writing examples based on Zynq

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Playing with Zynq Serial 37——[ex56] AXI HP bus reading and writing examples based on Zynq [Copy link]

1 Overview

The AXI HP bus is a very important function of the Zynq chip. It can realize high-throughput data communication between Cortex A9 and PL . It can be said that the biggest selling point of the Zynq chip is probably this bus. Sorry, it is not 1 , but 4 such AXI HP buses. As an AXI HP host, PL can read and write to the memory ( DDR3 ) through these 4 buses. The total maximum bandwidth of these 4 buses can usually exceed the maximum effective bandwidth of DDR3 . Therefore, for the data interaction between the processor and PL , the Zynq chip can achieve the optimal state. Therefore, for engineers who use Zynq for development, how to play with the AXI HP bus has become a compulsory course.

This example ( zstar_ex56 ) uses a simple AXI HP bus host read timing and write timing logic to guide readers to master the basic use of Zynq -based AXI HP bus. In this example, you first need to configure the AXI HP bus on the Zynq PS side , bring out the necessary interfaces in the system hardware block diagram, then instantiate the interface in the top-level source code, and perform the AXI HP read and write timing logic design.

2 Introduction to AXI Bus Protocol

Reference document "Playing with Zynq- Basics: Introduction to AXI Bus Protocol.pdf " .

3 AXI HP Configuration for Zynq PS

In ZYNQ7 Processing System , click the PS-PL Configuration page in the Page Navigator on the left , expand HP Slave AXI Interface --> S AXI HP0 Interface on the right , check S AXI HP0 Interface and select 64 as the data width behind the expanded S AXI HP0 DATA WIDTH (the only options are 32bit and 64bit ).

Back to the Diagram , you need to bring out the newly added S_AXI_HP0 interface. As shown in the figure, click S_AXI_HP0 , then right-click and click Create Interface Port... in the pop-up menu .

Name the interface AXI_HP0 as shown .

In the same way, lead out S_AXI_HP0_ACLK and name it AXI_HP0_ACLK . After the interface lead out is completed, it is as shown in the figure.

In the Address Editor , since the newly added AXI_HP0 bus address has not been mapped, as shown in the figure, you need to click Auto Assign Address on the left to perform automatic address assignment.

After completing the address mapping, as shown in the figure, AXI_HP0 is assigned a 1G memory space starting from the offset address ( Offset Address ) 0x0 by default. In other words, this 1G address space is the address space accessible by AXI_HP0 . Generally speaking, DDR3 will also be mapped to this address space by default. Then, DDR3 can be read and written through AXI_HP0 .

As shown in the figure, click Validate Design to confirm whether the current system configuration is OK .

4 AXI HP host read and write logic design

The hierarchical structure of the source code of this example project is as follows. We focus on the modules axi_hp0_source.v , axi_hp0_wr.v and axi_hp0_rd.v related to AXI HP .

The axi_hp0_source.v module counts and times in 1s units, and generates a set of 64-bit data with an increasing burst length = 16 to the fixed address 32'h0100_0000 of the AXI HP0 bus . The signal interface generated is as follows.

The o_data_* signals are sent to the axi_hp0_rd.v module to initiate a DDR3 read operation, and the i_data_* signals are sent to the axi_hp0_wr.v module to initiate a DDR3 write operation. In the ILA online logic analyzer, since there are read and write operations on the AXI HP0 bus every second, we can easily capture their timing for observation and analysis.

The axi_hp0_wr.v module generates the necessary timing for the signal interface of the write address channel, write data channel and write response channel of the AXI HP0 bus to complete the DDR3 write operation of a group of data. This module instantiates a FIFO named fifo_generator_0 . All the external data that needs to be written are sent to this module. When the state machine detects that the number of data in the FIFO meets the burst length of a DDR3 write , it initiates a DDR3 write address and data timing, reads the data in the FIFO , and sends it to DDR3 through the write data channel of AXI HP0 . The state relationship of executing the write operation is to write the address first ( STATE_WADD ), then send the data ( STATE_WDAT ), and finally wait for the write response ( STATE_DONE ), and complete an operation ( STATE_IDLE ).

The axi_hp0_rd.v module generates the necessary timing for the read address channel of the AXI HP0 bus. Since the read data channel is output by the slave, it is an input for this module. The purpose of this example is just to check the timing through the ILA online logic analyzer, so we did not make any additional connections to the interface of the read data channel. The design of this module is relatively simple. According to the timing pulse and address per second given by the axi_hp0_source.v module, a read address channel timing is generated per second.

5 AXI HP host read and write logic simulation

In the Sources of this example project , expand Simulation Sources --> sim_1 , and you can see the written test script tb_axi_hp0_wr.v , which mainly tests our AXI host write module axi_hp0_wr.v . The highlighted module in Simulation Sources indicates the currently valid top-level module.

If you want to change the valid top module in Simulation Sources , as shown in the figure, you can expand Flow Navigator --> Simulation and click Simulation Settings . In the pop-up tab, set Simulation top module name to the currently valid Simulation top module.

Click Simulation --> Run Simulation to execute the simulation of the test script.

As shown in the figure, after the simulation interface pops up, click the Run All button to run the simulation test.

The simulation waveform of the axi_hp0_wr.v module is as follows.

The timing waveform of the AXI HP0 bus writing address and data is shown in the figure.

6Embedded Software Engineering Creation

Refer to the document "Playing with Zynq- Tools: Exporting PS Hardware Configuration and Creating a New SDK Project.pdf " to export the PS hardware project, and open EDK to create a new HelloWorld template project. This example does not require any other functions to be implemented in the embedded software. You only need to run the embedded software after the .bit file is burned (mainly because the clock source of the PL end comes from the Zynq PS , so the clock signal can only be generated after the embedded software is running).

7. Board-level debugging

On the Zstar board, set jumper cap P3 to JTAG mode, that is, short-circuit PIN2-3 .

Connect the serial cable ( USB cable connects the USB port of PC and the UART interface of Zstar board ) and Xilinx download cable (downloader connects the USB port of PC and the JTAG socket of Zstar board ). Use 5V power supply to power the board.

Refer to the document "Playing with Zynq- Environment: XilinxPlatformCableUSB Downloader User Guide.pdf " to burn the .bit and .ltx files generated by the PL project compilation into the Zstar board, as shown in the figure.

Refer to "Playing with Zynq- Tools: SDK Online Running Naked Program.pdf " to export the hardware and open EDK to create a HelloWorld template project. Run the project. Note that the PL .bit file has been burned, so there is no need to burn it again. Just run the .elf file directly.

Go back to Vivado and view the currently exported AXI interface. As shown in the figure, you can double-click hw_ila_1 to pop up the dashboard_1 interface.

As shown in the figure, set AXI_wvalid == R as the trigger condition to trigger the waveform once.

After AXI_wvalid == R is triggered, as shown in the figure, two groups of waveform events appear. The first one is the AXI HP bus write data waveform, and the second one is the AXI HP bus read data waveform.

As shown in the figure, the first waveform continuously writes 16 64 -bit data incremented by 16 bits to the fixed address of the AXI bus .

As shown in the figure, the next waveform is an AXI bus read operation of the same address , and the 16 64 -bit data read out are consistent with the written data.

This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source